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| MC9S12P128_10 Datasheet, PDF (366/566 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers | |||
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Serial Communication Interface (S12SCIV5)
11.3.1 Module Memory Map and Register Deï¬nition
The memory map for the SCI module is given below in Figure 11-2. The address listed for each register is
the address offset. The total address for each register is the sum of the base address for the SCI module and
the address offset for each register.
11.3.2 Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register
diagram with an associated ï¬gure number. Writes to a reserved register locations do not have any effect
and reads of these locations return a zero. Details of register bit and ï¬eld function follow the register
diagrams, in bit order.
Register
Name
Bit 7
0x0000
R
SCIBDH1 W IREN
6
TNP1
5
TNP0
4
3
2
SBR12
SBR11
SBR10
1
SBR9
Bit 0
SBR8
0x0001
SCIBDL1
0x0002
SCICR11
R
SBR7
W
R
LOOPS
W
SBR6
SCISWAI
SBR5
RSRC
SBR4
M
SBR3
WAKE
SBR2
ILT
SBR1
PE
SBR0
PT
0x0000
R
0
0
0
0
SCIASR12
RXEDGIF
W
BERRV BERRIF BKDIF
0x0001
R
0
0
0
0
0
SCIACR12
RXEDGIE
W
BERRIE BKDIE
0x0002
R
0
0
0
0
0
SCIACR22 W
BERRM1 BERRM0 BKDFE
0x0003
R
SCICR2 W
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
0x0004
R TDRE
TC
RDRF
IDLE
OR
NF
FE
PF
SCISR1 W
0x0005
R
0
SCISR2
AMAP
W
0
RAF
TXPOL
RXPOL
BRK13
TXDIR
= Unimplemented or Reserved
Figure 11-2. SCI Register Summary (Sheet 1 of 2)
S12P-Family Reference Manual, Rev. 1.13
366
Freescale Semiconductor
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