MC68908GZ8MFJE Datasheet, PDF (80/314 Pages) Freescale Semiconductor, Inc – Microcontrollers

Configuration Register (CONFIG)
Address: $001F
Bit 7
6
5
4
Read:
COPRS
Write:
LVISTOP LVIRSTD LVIPWRD
Reset:
0
0
0
0
Note: LVI5OR3 bit is only reset via POR (power-on reset).
3
LVI5OR3
See note
2
SSREC
0
1
STOP
0
Figure 5-2. Configuration Register 1 (CONFIG1)
Bit 0
COPD
0
MSCANEN— MSCAN08 Enable Bit
Setting the MSCANEN enables the MSCAN08 module and allows the MSCAN08 to use the PTC0/PTC1
pins. See Chapter 12 MSCAN08 Controller (MSCAN08) for a more detailed description of the
MSCAN08 operation.
1 = Enables MSCAN08 module
0 = Disables the MSCAN08 module
NOTE
The MSCANEN bit is cleared by a power-on reset (POR) only. Other resets
will leave this bit unaffected.
TMCLKSEL— Timebase Clock Select Bit
TMCLKSEL enables an extra divide-by-128 prescaler in the timebase module. Setting this bit enables
the extra prescaler and clearing this bit disables it. See Chapter 4 Clock Generator Module (CGM) for
a more detailed description of the external clock operation.
1 = Enables extra divide-by-128 prescaler in timebase module
0 = Disables extra divide-by-128 prescaler in timebase module
OSCENINSTOP — Oscillator Enable In Stop Mode Bit
OSCENINSTOP, when set, will enable the oscillator to continue to generate clocks in stop mode. See
Chapter 4 Clock Generator Module (CGM). This function is used to keep the timebase running while
the reset of the MCU stops. See Chapter 18 Timebase Module (TBM). When clear, oscillator will cease
to generate clocks while in stop mode. The default state for this option is clear, disabling the oscillator
in stop mode.
1 = Oscillator enabled to operate during stop mode
0 = Oscillator disabled during stop mode (default)
ESCIBDSRC — SCI Baud Rate Clock Source Bit
ESCIBDSRC controls the clock source used for the serial communications interface (SCI). The setting
of this bit affects the frequency at which the SCI operates.See Chapter 15 Enhanced Serial
Communications Interface (ESCI) Module.
1 = Internal data bus clock used as clock source for SCI (default)
0 = External oscillator used as clock source for SCI
COPRS — COP Rate Select Bit
COPD selects the COP timeout period. Reset clears COPRS. See Chapter 6 Computer Operating
Properly (COP) Module
1 = COP timeout period = 2¹³ – 2⁴ COPCLK cycles
0 = COP timeout period = 2¹⁸ – 2⁴ COPCLK cycles
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
80
Freescale Semiconductor