MC68908GZ8MFJE Datasheet, PDF (71/314 Pages) Freescale Semiconductor, Inc – Microcontrollers

CGM Registers
VPR1 and VPR0 — VCO Power-of-Two Range Select Bits
These read/write bits control the VCO’s hardware power-of-two range multiplier E that, in conjunction
with L controls the hardware center-of-range frequency, f_VRS. VPR1:VPR0 cannot be written when the
PLLON bit is set. Reset clears these bits. (See 4.3.3 PLL Circuits, 4.3.6 Programming the PLL, and
4.5.5 PLL VCO Range Select Register.)
Table 4-4. VPR1 and VPR0 Programming
VPR1 and VPR0
E
00
0
01
1
10
2⁽¹⁾
1. Do not program E to a value of 3.
VCO Power-of-Two
Range Multiplier
1
2
4
NOTE
Verify that the value of the VPR1 and VPR0 bits in the PCTL register are
appropriate for the given reference and VCO clock frequencies before
enabling the PLL. See 4.3.6 Programming the PLL for detailed instructions
on selecting the proper value for these control bits.
4.5.2 PLL Bandwidth Control Register
The PLL bandwidth control register (PBWC):
• Selects automatic or manual (software-controlled) bandwidth control mode
• Indicates when the PLL is locked
• In automatic bandwidth control mode, indicates when the PLL is in acquisition or tracking mode
• In manual operation, forces the PLL into acquisition or tracking mode
Address:
Read:
Write:
Reset:
$0037
Bit 7
AUTO
0
6
5
LOCK
ACQ
0
0
= Unimplemented
4
3
2
0
0
0
0
0
0
R = Reserved
1
Bit 0
0
R
0
0
Figure 4-5. PLL Bandwidth Control Register (PBWC)
AUTO — Automatic Bandwidth Control Bit
This read/write bit selects automatic or manual bandwidth control. When initializing the PLL for manual
operation (AUTO = 0), clear the ACQ bit before turning on the PLL. Reset clears the AUTO bit.
1 = Automatic bandwidth control
0 = Manual bandwidth control
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
Freescale Semiconductor
71