MC68908GZ8MFJE Datasheet, PDF (226/314 Pages) Freescale Semiconductor, Inc – Microcontrollers

System Integration Module (SIM)
IAB
WAIT ADDR
WAIT ADDR + 1
SAME
SAME
IDB
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
Note: Previous data can be operand data or the WAIT opcode, depending on the
last instruction.
Figure 16-15. Wait Mode Entry Timing
Figure 16-16 and Figure 16-17 show the timing for WAIT recovery.
IAB
$6E0B
$6E0C $00FF $00FE $00FD $00FC
IDB $A6 $A6
$A6
$01
$0B
$6E
EXITSTOPWAIT
Note: EXITSTOPWAIT = RST pin or CPU interrupt
Figure 16-16. Wait Recovery from Interrupt
IAB
$6E0B
32
CYCLES
32
CYCLES
RSTVCTH RSTVCTL
IDB $A6 $A6
$A6
RST
CGMXCLK
Figure 16-17. Wait Recovery from Internal Reset
16.6.2 Stop Mode
In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a
module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset causes an exit from stop mode.
The SIM disables the clock generator module outputs (CGMOUT and CGMXCLK) in stop mode, stopping
the CPU and peripherals. Stop recovery time is selectable using the SSREC bit in the mask option register
(MOR). If SSREC is set, stop recovery is reduced from the normal delay of 4096 CGMXCLK cycles down
to 32. This is ideal for applications using canned oscillators that do not require long startup times from
stop mode.
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
226
Freescale Semiconductor