MC68908GZ8MFJE Datasheet, PDF (172/314 Pages) Freescale Semiconductor, Inc – Microcontrollers

Resets and Interrupts
ILAD — Illegal Address Reset Bit
1 = Last reset caused by an opcode fetch from an illegal address
0 = POR or read of SRSR since any reset
MODRST — Monitor Mode Entry Module Reset Bit
1 = Last reset caused by forced monitor mode entry.
0 = POR or read of SRSR since any reset
LVI — Low-Voltage Inhibit Reset Bit
1 = Last reset caused by low-power supply voltage
0 = POR or read of SRSR since any reset
14.3 Interrupts
An interrupt temporarily changes the sequence of program execution to respond to a particular event. An
interrupt does not stop the operation of the instruction being executed, but begins when the current
instruction completes its operation.
14.3.1 Effects
An interrupt:
• Saves the CPU registers on the stack. At the end of the interrupt, the RTI instruction recovers the
CPU registers from the stack so that normal processing can resume.
• Sets the interrupt mask (I bit) to prevent additional interrupts. Once an interrupt is latched, no other
interrupt can take precedence, regardless of its priority.
• Loads the program counter with a user-defined vector address
5
4
STACKING ³
ORDER ₂
1
•
•
•
CONDITION CODE REGISTER
ACCUMULATOR
INDEX REGISTER (LOW BYTE)⁽¹⁾
PROGRAM COUNTER (HIGH BYTE)
PROGRAM COUNTER (LOW BYTE)
•
•
•
1
2
3 _UNSTACKING
4
ORDER
5
$00FF DEFAULT ADDRESS ON RESET
1. High byte of index register is not stacked.
Figure 14-3. Interrupt Stacking Order
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
172
Freescale Semiconductor