MC68908GZ8MFJE Datasheet, PDF (145/314 Pages) Freescale Semiconductor, Inc – Microcontrollers

Programmer’s Model of Control Registers
Table 12-7. Baud Rate Prescaler
BRP5
0
0
0
0
:
:
1
BRP4
0
0
0
0
:
:
1
BRP3
0
0
0
0
:
:
1
BRP2
0
0
0
0
:
:
1
BRP1
0
0
1
1
:
:
1
BRP0
0
1
0
1
:
:
1
Prescaler
Value (P)
1
2
3
4
:
:
64
NOTE
The CBTR0 register can be written only if the SFTRES bit in the MSCAN08
module control register is set.
12.13.4 MSCAN08 Bus Timing Register 1
Address:
Read:
Write:
Reset:
$0503
Bit 7
6
5
4
3
2
1
SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11
0
0
0
0
0
0
0
Figure 12-19. Bus Timing Register 1 (CBTR1)
Bit 0
TSEG10
0
SAMP — Sampling
This bit determines the number of serial bus samples to be taken per bit time. If set, three samples per
bit are taken, the regular one (sample point) and two preceding samples, using a majority rule. For
higher bit rates, SAMP should be cleared, which means that only one sample will be taken per bit.
1 = Three samples per bit⁽¹⁾
0 = One sample per bit
TSEG22–TSEG10 — Time Segment
Time segments within the bit time fix the number of clock cycles per bit time and the location of the
sample point. Time segment 1 (TSEG1) and time segment 2 (TSEG2) are programmable as shown in
Table 12-8.
The bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of time
quanta (T_q) clock cycles per bit as shown in Table 12-4).
Pres value
Bit time =
• number of time quanta
f_MSCANCLK
NOTE
The CBTR1 register can only be written if the SFTRES bit in the MSCAN08
module control register is set.
1. In this case PHASE_SEG1 must be at least 2 time quanta.
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
Freescale Semiconductor
145