MC68908GZ8MFJE Datasheet, PDF (171/314 Pages) Freescale Semiconductor, Inc – Microcontrollers

Resets
14.2.3.4 Illegal Opcode Reset
An illegal opcode reset is an internal reset caused by an opcode that is not in the instruction set. An illegal
opcode reset sets the ILOP bit in the SIM reset status register.
If the stop enable bit, STOP, in the mask option register is a logic 0, the STOP instruction causes an illegal
opcode reset.
14.2.3.5 Illegal Address Reset
An illegal address reset is an internal reset caused by opcode fetch from an unmapped address. An illegal
address reset sets the ILAD bit in the SIM reset status register.
A data fetch from an unmapped address does not generate a reset.
14.2.4 System Integration Module (SIM) Reset Status Register
This read-only register contains flags to show reset sources. All flag bits are automatically cleared
following a read of the register. Reset service can read the SIM reset status register to clear the register
after power-on reset and to determine the source of any subsequent reset.
The register is initialized on power-up as shown with the POR bit set and all other bits cleared. During a
POR or any other internal reset, the RST pin is pulled low. After the pin is released, it will be sampled 32
CGMXCLK cycles later. If the pin is not above a V_IH at that time, then the PIN bit in the SRSR may be set
in addition to whatever other bits are set.
NOTE
Only a read of the SIM reset status register clears all reset flags. After
multiple resets from different sources without reading the register, multiple
flags remain set.
Address: $FE01
Bit 7
6
5
4
3
2
1
Bit 0
Read: POR
PIN
COP
ILOP
ILAD MODRST LVI
0
Write:
POR: 1
0
0
0
0
0
0
0
= Unimplemented
Figure 14-2. SIM Reset Status Register (SRSR)
POR — Power-On Reset Flag
1 = Power-on reset since last read of SRSR
0 = Read of SRSR since last power-on reset
PIN — External Reset Flag
1 = External reset via RST pin since last read of SRSR
0 = POR or read of SRSR since last external reset
COP — Computer Operating Properly Reset Bit
1 = Last reset caused by timeout of COP counter
0 = POR or read of SRSR since any reset
ILOP — Illegal Opcode Reset Bit
1 = Last reset caused by an illegal opcode
0 = POR or read of SRSR since any reset
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
Freescale Semiconductor
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