MC68908GZ8MFJE Datasheet, PDF (166/314 Pages) Freescale Semiconductor, Inc – Microcontrollers

Input/Output (I/O) Ports
READ DDRD ($0007)
WRITE DDRD ($0007)
RESET
WRITE PTD ($0003)
VDD
DDRDx
PTDx
PTDPUEx
READ PTD ($0003)
INTERNAL
PULLUP
DEVICE
PTDx
Figure 13-15. Port D I/O Circuit
When bit DDRDx is a logic 1, reading address $0003 reads the PTDx data latch. When bit DDRDx is a
logic 0, reading address $0003 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 13-5 summarizes the operation of the port D pins.
Table 13-5. Port D Pin Functions
PTDPUE
Bit
DDRD
Bit
PTD
Bit
I/O Pin
Mode
Accesses to DDRD
Read/Write
1
0
X⁽¹⁾
Input, V_DD(2)
DDRD7–DDRD0
0
0
X
Input, Hi-Z⁽⁴⁾
DDRD7–DDRD0
X
1
X
Output
DDRD7–DDRD0
1. X = Don’t care
2. I/O pin pulled up to V_DD by internal pullup device.
3. Writing affects data register, but does not affect input.
4. Hi-Z = High impedance
Accesses to PTD
Read
Write
Pin
PTD7–PTD0⁽³⁾
Pin
PTD7–PTD0⁽³⁾
PTD7–PTD0
PTD7–PTD0
13.6.3 Port D Input Pullup Enable Register
The port D input pullup enable register (PTDPUE) contains a software configurable pullup device for each
of the eight port D pins. Each bit is individually configurable and requires that the data direction register,
DDRD, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port
bit’s DDRD is configured for output mode.
Address: $000F
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PTDPUE7
Write:
Reset: 0
PTDPUE6
0
PTDPUE5
0
PTDPUE4
0
PTDPUE3
0
PTDPUE2
0
PTDPUE1
0
PTDPUE0
0
Figure 13-16. Port D Input Pullup Enable Register (PTDPUE)
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
166
Freescale Semiconductor