MC68908GZ8MFJE Datasheet, PDF (151/314 Pages) Freescale Semiconductor, Inc – Microcontrollers

Programmer’s Model of Control Registers
IDAM1–IDAM0— Identifier Acceptance Mode
The CPU sets these flags to define the identifier acceptance filter organization (see 12.5 Identifier
Acceptance Filter). Table 12-9 summarizes the different settings. In “filter closed” mode no messages
will be accepted so that the foreground buffer will never be reloaded.
Table 12-9. Identifier Acceptance Mode Settings
IDAM1
0
0
1
1
IDAM0
0
1
0
1
Identifier Acceptance Mode
Single 32-bit acceptance filter
Two 16-bit acceptance filter
Four 8-bit acceptance filters
Filter closed
IDHIT1–IDHIT0— Identifier Acceptance Hit Indicator
The MSCAN08 sets these flags to indicate an identifier acceptance hit (see
12.5 Identifier Acceptance Filter). Table 12-9 summarizes the different settings.
Table 12-10. Identifier Acceptance Hit Indication
IDHIT1
0
0
1
1
IDHIT0
0
1
0
1
Identifier Acceptance Hit
Filter 0 hit
Filter 1 hit
Filter 2 hit
Filter 3 hit
The IDHIT indicators are always related to the message in the foreground buffer. When a message gets
copied from the background to the foreground buffer, the indicators are updated as well.
NOTE
The CIDAC register can be written only if the SFTRES bit in the CMCR0 is
set.
12.13.10 MSCAN08 Receive Error Counter
Address: $050E
Bit 7
6
5
4
3
2
1
Read: RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1
Write:
Reset: 0
0
0
0
0
0
0
= Unimplemented
Figure 12-25. Receiver Error Counter (CRXERR)
Bit 0
RXERR0
0
This read-only register reflects the status of the MSCAN08 receive error counter.
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
Freescale Semiconductor
151