MC68908GZ8MFJE Datasheet, PDF (187/314 Pages) Freescale Semiconductor, Inc – Microcontrollers

Functional Description
15.4.2.1 Character Length
The transmitter can accommodate either 8-bit or 9-bit data. The state of the M bit in ESCI control
register 1 (SCC1) determines character length. When transmitting 9-bit data, bit T8 in ESCI control
register 3 (SCC3) is the ninth bit (bit 8).
15.4.2.2 Character Transmission
During an ESCI transmission, the transmit shift register shifts a character out to the TxD pin. The ESCI
data register (SCDR) is the write-only buffer between the internal data bus and the transmit shift register.
To initiate an ESCI transmission:
1. Enable the ESCI by writing a logic 1 to the enable ESCI bit (ENSCI) in ESCI control register 1
(SCC1).
2. Enable the transmitter by writing a logic 1 to the transmitter enable bit (TE) in ESCI control register
2 (SCC2).
3. Clear the ESCI transmitter empty bit (SCTE) by first reading ESCI status register 1 (SCS1) and
then writing to the SCDR. For 9-bit data, also write the T8 bit in SCC3.
4. Repeat step 3 for each subsequent transmission.
At the start of a transmission, transmitter control logic automatically loads the transmit shift register with
a preamble of logic 1s. After the preamble shifts out, control logic transfers the SCDR data into the
transmit shift register. A logic 0 start bit automatically goes into the least significant bit (LSB) position of
the transmit shift register. A logic 1 stop bit goes into the most significant bit (MSB) position.
The ESCI transmitter empty bit, SCTE, in SCS1 becomes set when the SCDR transfers a byte to the
transmit shift register. The SCTE bit indicates that the SCDR can accept new data from the internal data
bus. If the ESCI transmit interrupt enable bit, SCTIE, in SCC2 is also set, the SCTE bit generates a
transmitter CPU interrupt request.
When the transmit shift register is not transmitting a character, the TxD pin goes to the idle condition,
logic 1. If at any time software clears the ENSCI bit in ESCI control register 1 (SCC1), the transmitter and
receiver relinquish control of the port E pins.
15.4.2.3 Break Characters
Writing a logic 1 to the send break bit, SBK, in SCC2 loads the transmit shift register with a break
character. For TXINV = 0 (output not inverted), a transmitted break character contains all logic 0s and has
no start, stop, or parity bit. Break character length depends on the M bit in SCC1 and the LINR bits in
SCBR. As long as SBK is at logic 1, transmitter logic continuously loads break characters into the transmit
shift register. After software clears the SBK bit, the shift register finishes transmitting the last break
character and then transmits at least one logic 1. The automatic logic 1 at the end of a break character
guarantees the recognition of the start bit of the next character.
When LINR is cleared in SCBR, the ESCI recognizes a break character when a start bit is followed by
eight or nine logic 0 data bits and a logic 0 where the stop bit should be, resulting in a total of 10 or 11
consecutive logic 0 data bits. When LINR is set in SCBR, the ESCI recognizes a break character when a
start bit is followed by 9 or 10 logic 0 data bits and a logic 0 where the stop bit should be, resulting in a
total of 11 or 12 consecutive logic 0 data bits.
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
Freescale Semiconductor
187