MC68908GZ8MFJE Datasheet, PDF (73/314 Pages) Freescale Semiconductor, Inc – Microcontrollers

CGM Registers
4.5.4 PLL Multiplier Select Register Low
The PLL multiplier select register low (PMSL) contains the programming information for the low byte of
the modulo feedback divider.
Address:
Read:
Write:
Reset:
$0038
Bit 7
6
5
4
3
2
1
MUL7
MUL6
MUL5
MUL4
MUL3
MUL2
MUL1
0
1
0
0
0
0
0
Figure 4-7. PLL Multiplier Select Register Low (PMSL)
Bit 0
MUL0
0
NOTE
For applications using 1–8 MHz reference frequencies this register must be
reprogrammed before enabling the PLL. The reset value of this register will
cause applications using 1–8 MHz reference frequencies to become
unstable if the PLL is enabled without programming an appropriate value.
The programmed value must not allow the VCO clock to exceed 32 MHz.
See 4.3.6 Programming the PLL for detailed instructions on choosing the
proper value for PMSL.
MUL7–MUL0 — Multiplier Select Bits
These read/write bits control the low byte of the modulo feedback divider that selects the VCO
frequency multiplier, N. (See 4.3.3 PLL Circuits and 4.3.6 Programming the PLL.) MUL7–MUL0 cannot
be written when the PLLON bit in the PCTL is set. A value of $0000 in the multiplier select registers
configures the modulo feedback divider the same as a value of $0001. Reset initializes the register to
$40 for a default multiply value of 64.
NOTE
The multiplier select bits have built-in protection such that they cannot be
written when the PLL is on (PLLON = 1).
4.5.5 PLL VCO Range Select Register
NOTE
PMRS may be called PVRS on other HC08 derivatives.
The PLL VCO range select register (PMRS) contains the programming information required for the
hardware configuration of the VCO.
Address:
Read:
Write:
Reset:
$003A
Bit 7
6
5
4
3
2
1
VRS7
VRS6
VRS5
VRS4
VRS3
VRS2
VRS1
0
1
0
0
0
0
0
Figure 4-8. PLL VCO Range Select Register (PMRS)
Bit 0
VRS0
0
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
Freescale Semiconductor
73