MC68908GZ8MFJE Datasheet, PDF (247/314 Pages) Freescale Semiconductor, Inc – Microcontrollers

I/O Registers
The CPU can always read the state of the SS pin by configuring the appropriate pin as an input and
reading the port data register. See Table 17-3.
SPE SPMSTR
0
X⁽¹⁾⁾
1
0
1
1
1
1
1. X = Don’t care
Table 17-3. SPI Configuration
MODFEN
SPI Configuration
X
Not enabled
X
Slave
0
Master without MODF
1
Master with MODF
State of SS Logic
General-purpose I/O;
SS ignored by SPI
Input-only to SPI
General-purpose I/O;
SS ignored by SPI
Input-only to SPI
17.12.5 CGND (Clock Ground)
CGND is the ground return for the serial clock pin, SPSCK, and the ground for the port output buffers. It
is internally connected to V_SS as shown in Table 17-1.
17.13 I/O Registers
Three registers control and monitor SPI operation:
• SPI control register (SPCR)
• SPI status and control register (SPSCR)
• SPI data register (SPDR)
17.13.1 SPI Control Register
The SPI control register:
• Enables SPI module interrupt requests
• Configures the SPI module as master or slave
• Selects serial clock polarity and phase
• Configures the SPSCK, MOSI, and MISO pins as open-drain outputs
• Enables the SPI module
Address: $0010
Bit 7
6
5
4
3
2
1
Read:
SPRIE
Write:
R
SPMSTR CPOL CPHA SPWOM SPE
Reset: 0
0
1
0
1
0
0
R = Reserved
Figure 17-14. SPI Control Register (SPCR)
Bit 0
SPTIE
0
SPRIE — SPI Receiver Interrupt Enable Bit
This read/write bit enables CPU interrupt requests generated by the SPRF bit. The SPRF bit is set
when a byte transfers from the shift register to the receive data register. Reset clears the SPRIE bit.
1 = SPRF CPU interrupt requests enabled
0 = SPRF CPU interrupt requests disabled
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
Freescale Semiconductor
247