MC68908GZ8MFJE Datasheet, PDF (69/314 Pages) Freescale Semiconductor, Inc – Microcontrollers

CGM Registers
Addr.
Register Name
Bit 7
6
5
$0036
PLL Control Register ^Read:
(PCTL) Write:
See page 69. _Reset:
PLLIE
0
PLLF
PLLON
0
1
PLL Bandwidth Control ^Read: _AUTO
LOCK
ACQ
$0037
Register (PBWC) Write:
See page 71. _Reset:
0
0
0
PLL Multiplier Select High ^Read:
0
0
0
$0038
Register (PMSH) Write:
See page 72. _Reset:
0
0
0
$0039
PLL Multiplier Select Low ^Read:
Register (PMSL) Write:
See page 73. _Reset:
MUL7
0
MUL6
1
MUL5
0
$003A
PLL VCO Select Range ^Read:
Register (PMRS) Write:
See page 73. _Reset:
VRS7
0
VRS6
1
VRS5
0
Read: 0
0
0
$003B
Reserved Register Write:
Reset: 0
0
0
= Unimplemented
NOTES:
1. When AUTO = 0, PLLIE is forced clear and is read-only.
2. When AUTO = 0, PLLF and LOCK read as clear.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
4
3
2
BCS
R
R
0
0
0
0
0
0
0
0
0
0
MUL11 MUL10
0
0
0
MUL4
MUL3
MUL2
0
0
0
VRS4
VRS3
VRS2
0
0
0
0
R
R
0
0
0
R = Reserved
Figure 4-3. CGM I/O Register Summary
1
VPR1
0
0
0
MUL9
0
MUL1
0
VRS1
0
R
0
Bit 0
VPR0
0
R
0
MUL8
0
MUL0
0
VRS0
0
R
1
4.5.1 PLL Control Register
The PLL control register (PCTL) contains the interrupt enable and flag bits, the on/off switch, the base
clock selector bit, and the VCO power-of-two range selector bits.
Address:
Read:
Write:
Reset:
$0036
Bit 7
PLLIE
0
6
5
4
3
2
PLLF
PLLON
BCS
R
R
0
1
0
0
0
= Unimplemented
R
= Reserved
Figure 4-4. PLL Control Register (PCTL)
1
VPR1
0
Bit 0
VPR0
0
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
Freescale Semiconductor
69