MC33780 Datasheet, PDF (8/37 Pages) Freescale Semiconductor, Inc – Dual DBUS Master with Differential Drive and Frequency Spreading

DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 4.75 V ≤ V_CC ≤ 5.25 V, 9.0 V ≤ V_SUP ≤ 25 V, -40°C ≤ T_A ≤ 85°C unless otherwise
noted. Voltages relative to GND unless otherwise noted. Typical values noted reflect the approximate parameter means at
T_A = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
BUS TRANSMITTER
Idle-to-Signal and Signal-to-Idle Slew Rate (12 ≤ V_SUP ≤ 25 V) ⁽⁸⁾
Signal High-to-Low and Signal Low-to-High Slew Rate ^{(8), (11)}
(See Data Valid DSIS to DnD Timing)
t_{SLEW (IDLE)}
t_{SLEW (SIGNAL)}
Communication Data Rate Capability ⁽¹¹⁾ (Ensured by Transmitter Data
Valid and Receiver Delay Measurements)
D_RATE
Signal Bit Time (1 / D_RATE) ⁽¹¹⁾
t_BIT
INT Turn ON Delay, DBUS Transaction End to Receive FIFO
INT Low ^{(9), (13)}
t_INTON
INT Turn ON Delay (C = 100 pF) ⁽¹⁰⁾
CS to INT Low
t_INTON
2.0
3.0
–
6.67
–
–
4.5
8.0
V/µs
4.5
8.0
V/µs
–
150
kbps
–
–
µs
–
1/3 * tBIT
µs
+0.2
µs
–
0.2
INT Turn OFF Delay, CS/SCLK Rising Edge to INT High
DBUS Start Delay, CS/SCLK Rising Edge to DBUS ^{(9), (11), (13)}
Spread Spectrum Mode Disabled
Spread Spectrum Mode Enabled
Data Valid ^{(8), (10)}
DSIF (CS) = 0.5 * V_CC to DnD Fall = 5.5 V
DSIS (MOSI) = 0.5 * V_CC to DnD Fall = 0.2 * ∆V_DnD ⁽¹²⁾
DSIS (MOSI) = 0.5 * V_CC to DnD Rise = 0.8 * ∆V_DnD ⁽¹²⁾
DSIF (CS) = 0.5 * V_CC to DnD Rise = 6.5 V
t_INTOFF
–
–
0.2
µs
µs
t_DBUSSTART1
1/3 * t_BIT
–
2/3 * t_BIT
t_DBUSSTART2
1/3 * t_BIT
–
4/3 * t_BIT
µs
t_DVLD1
–
6.0
6.56
t_DVLD2
0.25
0.8
1.3
t_DVLD3
0.25
0.8
1.3
t_DVLD4
–
0.8
1.3
Signal Driver Overcurrent Shutdown Delay
t_OC
2.0
–
20
µs
Signal Low Time for Logic Zero
33.3% Duty Cycle ⁽¹⁴⁾
t0_LO
µs
2/3 * t_BIT-0.8 2/3 * t_BIT-0.6 2/3 * t_BIT-0.4
Signal Low Time for Logic One
66.7% Duty Cycle ⁽¹⁴⁾
t1_LO
µs
1/3 * t_BIT-0.8 1/3 * t_BIT-0.6 1/3 * t_BIT-0.4
Notes
8. C = 7.5 nF from DnH to DnL and 4.7 nF from DnH and DnL to GND, capacitor tolerance = ±10%.
9. In the case where the SPI write to DnL (initiating a DBUS transaction start or causing an interrupt) is the last byte in the burst sequence,
timing is from rising edge of CS. Otherwise, timing is from the first SCLK rising edge of the next SPI burst byte.
10. Delays are measured in test mode to determine the delay for analog signal paths.
11. Not measured in production.
12. ∆V_DnD = V_DnD(HIGH) - V_DnD(LOW).
13. Internal digital delay only.
14. Guaranteed by design.
33780
8
Analog Integrated Circuit Device Data
Freescale Semiconductor