MC33780 Datasheet, PDF (15/37 Pages) Freescale Semiconductor, Inc – Dual DBUS Master with Differential Drive and Frequency Spreading

FUNCTIONAL DESCRIPTIONS
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
PROTOCOL ENGINE
This block converts the data to be transmitted from the
registers into the DBUS sequences, and converts DBUS
response sequences to data in the registers. It generates the
proper DBUS timing.
The DBUS transmit protocol uses a return to 1 type data
with a duty cycle determined by the logic state. The protocol
requires Cyclical Redundancy Check (CRC) generation and
validation.
DSIR
Comp.
Idle
DSIS
Differential
Signal
Generation
Signal
Signal
Common
Mode
Correction
DnH
DnL
Idle
DSIF
Control
Overvoltage T_LIM
Figure 10. Driver/Receiver Block Diagram
DBUS DRIVER /RECEIVER (PHYSICAL LAYER)
This block translates the transmit data to the voltage and
current needed to drive the DBUS. It also detects the
response current from the slave devices and translates that
current into digital levels. These circuits can drive their
outputs to the levels listed in Table 5.
The internal signal DSIF controls the Idle to Signalling
state change, and internal signal DSIS controls the signal
level, high or low. DSIR is the slave device response signal to
the logic. This is shown in Table 6.
Table 6. Internal Signal Truth Table
DSIF
0
DSIS
0
T_LIM
0
DSIR
Return Data
DnD
Signal Low
0
1
0
Return Data Signal High
1
0
0
0
High Impedance
1
1
0
0
Idle
X
X
1
0
High Impedance
The DBUS driver block diagram is shown in Figure 10. The
circuit uses independent drivers for the Idle and Signal states.
This allows each driver to be optimized for its function. The
Idle driver is active in Idle and during the transitions from Idle
to Signal high and Signal high to Idle. The Signal driver is only
active during actual signaling. Both drivers are disabled in
HiZ.
The Idle driver is required to supply a high current to
recharge the Slave device storage capacitors. It is also
required to drive the DBUS load capacitances and control the
slew rate over a wide supply voltage range. The DnH and
DnL Idle drivers are each optimized for their specific drive
requirements.
The Signal driver is optimized for driving the DBUS load,
and has the requirement of good slew rate control and
stability over a wide range of load conditions. The DnH and
DnL outputs use identical Signal driver circuits.
To ensure stability of the Signal driver, capacitors must be
connected between each output and ground. These are the
DBUS common mode capacitors. In addition, a bypass
capacitor is required at V_SUP. These capacitors must be
located close to the IC terminals and provide a low
impedance path to ground.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33780
15