MC33780 Datasheet, PDF (20/37 Pages) Freescale Semiconductor, Inc – Dual DBUS Master with Differential Drive and Frequency Spreading

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Users initiate a message by writing (via the SPI interface
from the MCU) to the low byte of the data register (DnL).
When 9- to 16-bit messages are to be sent, the user writes to
the DnH register first and then the DnL register before the
combined 9 to 16-bit data value DnH:DnL is sent on the
DBUS. The user should first check the TFNFn status flag to
be sure the transmit FIFO is not full before writing a new data
value to DnH and/or DnL. When the minimum inter-frame
delay has been satisfied, the DSIF terminal will go low,
indicating the start of a new transfer frame.
DBUS Driver/Receiver communications involve a frame
(DSIF), a data signal (DSIS), and a data return (DSIR) signal.
These are signals internal to the IC associated with the
prData is shifted out of DSIS (MSB first) and shifted into DSIR
at the same time. As a message is received, it is stored bit-
by-bit into the next available receive FIFO location. For each
data value in the receive FIFO, there is a one-bit status flag
to indicate whether or not there was a CRC error while
receiving the data. At the end of a DBUS transfer (and after
the CRC error status is stable), the RFNEn flag is set (if it was
not already) to indicate there is data in the receive FIFO to be
read.
DATA RATE
In non-spread spectrum mode, the data rate is determined
by the system clock (CLK) and the programmable clock
divider. (The Clock Divider ratio n is defined in Table 10.)
Data Rate = f_CLK / (27 * n)
In spread spectrum mode, the data rate is determined by
the system clock (CLK) and the DnOFFSETL/H register
programming. Note the programmable clock divider does not
control the data rate in Spread Spectrum mode. Refer to
Register and Bit Descriptions section for details.
The following table gives the correspondence between the
offset and the data rate for f_CLK = 4.0 MHz.
Table 7. Data Rate versus OFFSET (Spread Spectrum)
OFFSET
HEX
DEC
Data Rate
kHz
00
0
121.2
3F
63
136.1
7A
122
150.1
9F
159
158.9
For other clock frequencies, the data rate can be
computed using the following formula:
Data Rate = (f_CLK / 33) * (1 + OFFSET / 512)
CRC GENERATION /CHECKING
Whenever a message is sent on the DBUS, a 0- to 8-bit
CRC value is computed and serially sent as the next n bits
after the LSB of the data. The CRC length, polynomial, and
initial seed are determined by the CRCLEN[3:0],
CRCPOLY[7:0], and CRCSEED[7:0] control register fields.
The message, including the CRC bits, is passed along to a
remote peripheral, which computes a separate CRC value as
the message data is received. If this computed CRC does not
agree with the CRC value received in the message, the
peripheral device considers the message invalid.
Messages received include a 0- to 8-bit CRC value, which
was computed in the peripheral device that is responding. As
the message is received, a separate 0- to 8-bit CRC value is
computed and is compared with the CRC value in the
received message. If these values do not agree, the message
is considered invalid and the ERn status bits in the D01STAT
register are set as the receive data is transferred into the
receive data buffer.
When no remote peripheral responds to a message, the
data pattern received will be all zeros with a CRC value of 0,
which may be detected as a CRC error depending on the
values of CRCLEN[3:0], CRCPOLY[7:0], and
CRCSEED[7:0]. On the other hand, if a remote peripheral is
attached and responds with all zeros with a CRC value of
1010, this may be detected as a non-error condition.
CRC COMPUTATION
The CRC algorithm uses a programmable initialization
value, or seed, of CRCSEED[7:0] and a programmable
polynomial of CRCPOLY[7:0]. Figure 16 is a VHDL
description of the CRC algorithm for the DBUS standard 4-bit
CRC with its initial value of 1010. A seed value is chosen so
that a zero data value will generate a CRC value of 1010. A
block diagram of the default CRC calculation is shown in
Figure 17.
33780
20
Analog Integrated Circuit Device Data
Freescale Semiconductor