MC33780 Datasheet, PDF (28/37 Pages) Freescale Semiconductor, Inc – Dual DBUS Master with Differential Drive and Frequency Spreading

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
DLYn[B:A]
MSn
DBUS Encode/Decode Logic
Rx FIFOn
DnH Rx DnL Rx ERn
Tx FIFOn
DnH Tx DnL Tx
(Read-Only)
(Write-Only)
DnSTAT Register
(Read-Only)
TFEn
TIEn
RFNEn
RIEn
DnCTRL Register
4 Interrupt Sources
(2 shown)
Interrupt Request
DEN Register
Figure 24. DBUS Master Registers and Interrupt Block Diagram
DnH REGISTERS
These are read/write registers. There are two of these
registers, one for each of the buses, as shown in Figure 24.
When written to, the data is the high byte of a 9- to16-bit
command. When read, it is the high byte of a 9- to 16-bit
return on the DBUS. Writing to this register does not begin a
DBUS transaction. The low byte must be written to initiate the
DBUS transaction.
SPI Data Bit
Bit 7
6
5
The bit assignments are shown in Figure 25. When a short
word of 8 bits is selected for the DBUS (MSn = 1), this register
is skipped in the SPI burst sequence. When the short word
length is set at other than 8 bits, this register will contain the
bits above eight, starting with the ninth bit in the least
significant bit position of the register. Unused bit positions are
don’t care values.
4
3
2
1
0
Read / Write
Reset
Bit 15
0
Bit 14
0
Bit 13
0
Bit 12
0
Bit 11
0
Bit 10
0
Bit 9
0
Bit 8
0
Figure 25. DnH Data Register Bit Assignments
33780
28
Analog Integrated Circuit Device Data
Freescale Semiconductor