MC33780 Datasheet, PDF (18/37 Pages) Freescale Semiconductor, Inc – Dual DBUS Master with Differential Drive and Frequency Spreading

FUNCTIONAL DESCRIPTIONS
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
have been made. After the fast acquisition, the PLL switches
automatically to a slow acquisition mode (180.224 ms per
update cycle, based on 4.0 MHz clock).
SPREADER LOGIC
The Spreader Logic contains a pseudo-random binary
sequence (PRBS) generator and time compensation
circuitry. The PRBS can generate maximal length sequences
of 6, 7, 11, and 15 bits. Maximal length means there is no
repeat of the sequence until 2ⁿ counts have been reached,
where n is the selected length.
A special feature of the Spreader Logic is that the bit
periods are chosen in a way to keep the length of the frame
constant, provided that the total number of bits is even. This
is useful if the time between samples made by the slaves
must be kept relatively constant. Without this feature, the time
from sample-to-sample would vary randomly.
The DEV1 and DEV0 bits in the DnSSCTRL register
control whether the deviation is enabled or disabled.
The Spreader Logic is synchronized to only change the
value of the digital word to the Spreader DAC at the
beginning of a DBUS bit. When spreading is enabled, these
changes will occur once per DBUS bit-time.
33780
18
Analog Integrated Circuit Device Data
Freescale Semiconductor