MC33780 Datasheet, PDF (25/37 Pages) Freescale Semiconductor, Inc – Dual DBUS Master with Differential Drive and Frequency Spreading

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Figure 21 describes what happens during DBUS serial
transfers. State transfers in this state machine are
synchronous with positive edges on the scaled DBUS 1/3rd
bit clock and the initial state is WAIT_FRAME_DLY. Initial
entry into this state is caused by a reset, abort, or by enable
becoming inactive. These conditions cause an asynchronous
entry into this state. The exit to the next state,
WAIT_SIG_DLY_0, needs to be synchronous.
When enable is true and there is at least one valid entry in
the transmit FIFO, the DBUS frame signal is driven low to
start a frame. States WAIT_SIG_DLY_0 through
WAIT_SIG_DLY_2 create a one DBUS bit-time delay before
the start of the first data bit. After WAIT_SIG_DLY_2, the
DBUS_BIT_PTR gets initialized to the total word length, as
determined by the MSx, SWLENx, and CRCLENx bits. The
XFER_DBUS_BIT_0 state is then entered.
XFER_DBUS_BIT_0 through XFER_DBUS_BIT_2 form a
loop where each pass corresponds to one DBUS bit time.
During the first third of the bit the DSIxS signal is low, during
the second third DSIxS is low for a zero or high for a one,
during the last third of the bit time DSIxS is high. Provided this
is not the end of the last CRC bit, the bit pointer is
decremented and the loop is repeated.
After the last CRC bit, the DBUS_R_PUSH state is
entered. This state ensures that the CRC flag is stable prior
to adjusting the receive (and transmit) FIFO pointers. The
DBUS_X_POP state prevents an X_FIFO_POP from
occurring at the same time as an R_FIFO_PUSH.
After DBUS_X_POP, the state transitions back to the
WAIT_FRAME_DLY state. This state ensures proper frame
spacing is allowed to charge up the storage capacitors in
remote nodes. Notice that the delay counter was reset at the
end of the last CRC bit so the delay period can start to time
out even while the DBUS_R_PUSH and DBUS_X_POP
states are being processed.
Figure 22 describes the operation of the transmit FIFO.
This FIFO is four levels deep, including the stage which is
written into by the SPI and the stage which provides the data
for the current DBUS serial transfer. State transitions in this
state machine occur at the trailing edges of X_FIFO_PUSH
and X_FIFO_POP.
When this FIFO is completely empty, the SPI can write
four new values to fill the FIFO without waiting for any action
on the DBUS side of the FIFO. Values are pushed into the
FIFO from the SPI interface and values are popped after they
have been serially sent out of the DBUS interface. When the
FIFO is full, additional attempts to write new data from the
SPI side are ignored (the host MCU should be sure the
TFNFx status bit is set before writing more data to the FIFO).
Reset, abort, or enable going to zero causes
asynchronous entry to the TX_IDLE state, which
corresponds to the FIFO empty condition. The push and pop
pointers are cleared and X_FIFO_EMPTY is set to true.
X_FIFO_PUSH causes the push pointer to be incremental,
X_FIFO_EMPTY to be set to false, and the state to transition
to TX_NOT_EMPTY. The push request comes from the SPI
transfer state machine after a new value has been written into
the FIFO.
RSTB ACTIVE or ABORT or ~EN/
RESET_DELAY_CNTR;
DSIF = 1, DSIS = 1;
STATE TRANSISITONS OCCUR
ON POS EDGE OF SCALED
DBUS 1/3^RD BIT CLOCK
WAIT_FRAME_DLY
DELAY_OVER &
X_FIFO_NOT_EMPTY/
DSIF = 0;
WAIT_SIG_DLY[0..2] CAUSES 1 BIT-TIME DLY TO 1^ST BIT FALLING EDGE
WAIT_SIG_DLY_0
WAIT_SIG_DLY_1
WAIT_SIG_DLY_2
DBUS_BIT_PTR = 8 to 15, OR 23;
DSIS = 0;
~LAST_CRC_BIT/
DBUS_BIT_PTR = DBUS_BIT_PTR-1;
DSIS = 0;
XFER_DBUS_BIT_0
XFER_DBUS_BIT_1
XFER_DEBUS_BIT_2
DSIS = DATA;
DSIS = 1;
X_FIFO_POP = 0;
R_FIFO_PUSH = 0;
DBUS_X_POP
DBUS_R_PUSH
Figure 21. State Diagram of DBUS Transfer
LAST_CRC-BIT/
DSIF = 1, DSIS = 1;
RESET DELAY_CNR;
R_FIFO_PUSH = 1
X_FIFO_POP = 1;
Analog Integrated Circuit Device Data
Freescale Semiconductor
33780
25