MC33780 Datasheet, PDF (16/37 Pages) Freescale Semiconductor, Inc – Dual DBUS Master with Differential Drive and Frequency Spreading

FUNCTIONAL DESCRIPTIONS
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
The DSIF signal controls the state of the drivers, enabling
the Idle drivers or Signal drivers as is appropriate. A
comparator in the Control block compares the DnL output
voltage with the internal Signal high voltage to determine the
transition from Idle driver to Signal driver. The overvoltage
signal modifies the driver characteristics. This is described in
more detail in the Load Dump Operation section.
The overtemperature signal is also applied to this block.
The Differential Signal Generation block converts the
DSIS signal to the DBUS differential signal voltage levels.
This differential signal is buffered and slew rate controlled by
the Signal drivers. This block is active in all driver modes.
A special requirement of the differential bus is to maintain
a low common mode voltage. This is especially important
during the Idle to Signal transition in order to produce a
smooth changeover to the Signal driver. This is accomplished
by monitoring the common mode voltage and modifying the
Idle driver slew rates. This is the function of the Common
Mode Correction block. An additional feature to make a
smooth changeover and minimize undershoot is to reduce
the slew rate as the changeover point is approached. This
block is not illustrated in Figure 10.
A sense resistor between the Signal driver and the DnH
output detects the Slave device response current. A
comparator (Comp.) generates the signal DSIR that is
supplied to the logic.
The comparator consists of a sense amplifier with offset
(V_OS), a filter capacitor and logic gate with buffers to produce
the logic signal (DSIR). The sense amplifier is a ‘gm’ stage
that amplifies the voltage across the sense resistor (R_S) to
produce an output current that charges and discharges a filter
capacitor. The voltage across the filter capacitor is compared
with the threshold voltage of the logic gate to produce the
output signal. The voltage across the filter capacitor is
clamped between VCC and ground. See Figure 11.
R_S
I_BUS
DnH
V_OS
I_O
gm
V_TH
DSIR
C
Figure 11. Receive Filter
Definitions
• C = value of filter capacitor = 2.0 pF
• V_TH = threshold of logic gate = V_CC/2 = 2.5 V
• A = current gain from sense resistor to filter capacitor =
I_O/I_BUS = 3.0 µA/mA (the amplifier saturates with an
output current of ±40 µA)
• I_BUS[mA] = bus response current.
• I_TH[mA] = response current threshold = V_OS/R_S = 6
The filter delay time is given by:
t[µs] = (C * V_TH)/A(I_BUS-I_TH) = 1.7/(I_BUS-I_TH)
The filter characteristic can also be expressed as the
product of the overdrive current (I_BUS-I_TH) and the duration of
the interference pulse, which must be less than 1.7 µs * mA
for the interference to be filtered.
33780
16
Analog Integrated Circuit Device Data
Freescale Semiconductor