MC33780 Datasheet, PDF (19/37 Pages) Freescale Semiconductor, Inc – Dual DBUS Master with Differential Drive and Frequency Spreading

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
SPI COMMUNICATIONS
All SPI transactions start with a command byte and can be
followed by 1 or more bytes of data. The start of an SPI
transaction is signaled by CS being asserted low. The first bit
sent (bit 7) of the first byte signals a read or write (write = 1)
of data. The last five bits (bits 4–0) of the command set a
Bit 7
6
R/W
X
5
4
X
ADDR4
pointer to the desired register. Bits 5 and 6 are unused. See
Figure 13. As long as CS is asserted low, each additional byte
sent over the SPI will be a read/write of data to the sequential
next register. After address 10101 is written to, the next write
will wrap around to address 00000.
3
ADDR3
2
ADDR2
1
ADDR1
0
ADDR0
Figure 13. SPI Communications, First Byte of Burst Transfer
The receive FIFO is popped only when the SPI reads or
writes the low data register (DnL). The Control and Status
registers can be read without affecting the receive FIFO. The
transmit FIFO is popped at the end of the DBUS transaction.
Figure 14 shows an example of a write operation. This
example assumes the last SPI transaction read or wrote the
data from register 00011 and is now pointing at 00100
(D01STAT). During the first byte of the SPI transaction, the
first MOSI bit is 1 (write) and the last five are 00000. During
this command byte, MISO returns the data from register
00100 (D01STAT). During the next SPI transactions, MOSI
updates the data in register 00000 with new data while
reading back the old data via MISO.
Although it looks like the read and write for an address are
occurring at the same time, the changes caused earlier
during the same burst would not be reflected by the data
returned, because the D01STAT is latched at CS going low.
When a short word is selected for Bus 0 (MS0 in D0CTRL
is set), the D0H register is skipped in the sequence. The
same is true for the D1H register when MS1 is set and
SWLEN1 = 1000.
SCCLLKK
MOS I
MI SO
C S_CB_S
WWRRITITEE CCOOMMMMANADN D
P ^PO^OIN^INT^T T^TOO⁰0⁰0⁰⁰0⁰0 0
DDAATTA FFRROOMM
D S^DI⁰0¹1^SS^TAT^TA⁽T⁰(⁰0¹0⁰1⁾0 0)
DADATTAATTOO DD0SHI0 H
(⁽0⁰⁰0⁰0⁰0⁰0⁾ )
DDATAATFAROFMR OD0MH
D SI 0(0H00(0000) 000 )
D ADTAATATTOO DD0SLI 0L
(⁽0⁰⁰0⁰0⁰0¹⁾1)
DDAATAT AFRFORMODM0L
D SI0⁽⁰L⁰⁰(0¹0⁾0 01 )
D ADTAATATTOO D1SHI 1H
(⁽0⁰⁰0⁰0¹1⁰0⁾ )
D^DAT^AA^TF^AR^FO^RM^OD^M1H
DS I1(H000(1000)01 0)
DADTAATATTOODD1SLI1 L
(0⁽⁰0⁰0⁰¹1¹1⁾ )
DDATAAT FARFORM OD1ML
D SI 1(0L00(0101)01 1)
Figure 14. SPI Burst Transfer Example
DBUS COMMUNICATIONS
The DBUS messages contain data from the DnH and DnL
registers. A CRC pattern is automatically appended to each
message. The data and CRC lengths are programmed by the
DnLENGTH register. Figure 15 shows the structure of the
DBUS message.
Bit n
. . . . . . . . . . . . . . . ..
Bit 0
CRC n
.....
CRC 0
Figure 15. DBUS Communications Message
DBUS Driver/Receiver communications involve a frame
(DSIF), a data signal (DSIS), and a data return (DSIR) signal.
These are signals internal to the IC associated with the
protocol engine.
A message starts with a falling edge on the DSIF signal,
which marks the start of a frame. There is a one bit-time delay
before the MSB of data appears on the DSIS terminal. Data
bits start with a falling edge on DSIS. The low time is 1/3 of
the bit time for a 1, and 2/3 of a bit time for a 0. Data is
transmitted on DSIS and received on DSIR terminals
simultaneously. Receive data is the captured level on the
DSIR terminal at the end of each bit time. At the end of the bit
time for the last CRC bit, the DSIF terminal returns to a logic
high (Idle level). A minimum delay is imposed between
successive frames as determined by the DnCTRL register.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33780
19