MC33780 Datasheet, PDF (7/37 Pages) Freescale Semiconductor, Inc – Dual DBUS Master with Differential Drive and Frequency Spreading

DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 4.75 V ≤ V_CC ≤ 5.25 V, 9.0 V ≤ V_SUP ≤ 25 V, -40°C ≤ T_A ≤ 85°C unless otherwise
noted. Voltages relative to GND unless otherwise noted. Typical values noted reflect the approximate parameter means at
T_A = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
CLOCK
CLK Periods
Time High
Time Low
Period (System requirement) ⁽⁶⁾
CLK Transition (System requirement) ⁽⁶⁾
Time for Low-to-High Transition of the CLK Input Signal
Time for High-to-Low Transition of the CLK Input Signal
Reset Low Time
ns
tCLKHI
75
–
–
tCLKLO
75
–
–
tCLKPER
245
250
255
tCLKLH
–
tCLKHL
–
ns
–
50
–
50
tRSTLO
100
–
–
ns
SPI INTERFACE TIMING
SPI Clock Cycle Time
tCYC
200
–
–
ns
SPI Clock High Time
tHI
80
–
–
ns
SPI Clock Low Time
SPI CS Lead Time ⁽⁷⁾
SPI CS Lag Time ⁽⁷⁾
SPI SCLK Time Between Bytes ⁽⁶⁾
SPI CS Time Between Bursts ⁽⁶⁾
Data Setup Time
MOSI Valid Before SCLK Rising Edge ⁽⁷⁾
tLO
80
–
tLEAD
100
–
tLAG
100
–
tHI
80
–
t_CSHI
80
–
tSU
25
–
–
ns
–
ns
–
ns
–
ns
–
ns
ns
–
Data Hold Time
MOSI Valid After SCLK Rising Edge ⁽⁷⁾
MISO Valid After SCLK Falling Edge ⁽⁶⁾
ns
tH
25
–
–
tHO
0
–
–
Data Valid Time
SCLK Falling Edge to MISO Valid, C = 100 pF
t_V
ns
–
–
50
Output Disable Time
CS Rise to MISO Hi-Z
Rise Time (30% V_CC to 70% V_CC) ⁽⁶⁾
SCLK, MISO
Fall Time (70% V_CC to 30% V_CC) ⁽⁶⁾
SCLK, MISO
t_DIS
ns
–
–
100
t_R
ns
–
–
25
t_F
ns
–
–
25
Notes
6. Not measured in production.
7. SPI signal timing from the production test equipment is programmed to ensure compliance.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33780
7