MC33780 Datasheet, PDF (24/37 Pages) Freescale Semiconductor, Inc – Dual DBUS Master with Differential Drive and Frequency Spreading

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
ASYNCHRONOUS RESET/
ACTION(S);
IDLE
STATE TRANSITIONS OCCUR
ON POS EDGE OF XXX CLK
STATE_1
SYNCHRONOUS CONDITIONS/
ACTION(S);
Figure 19. State Diagram Notation
Figure 20, describes how SPI transfers lead to transmit
FIFO push operations or transfer abort actions. State
transitions in this state machine are synchronous with rising
edges of the SPI clock (SCLK). The initial state, SPI_IDLE, is
entered asynchronously whenever internal reset becomes
active or the SPI chip select (CS) input is de-asserted. Upon
entry to the idle state, the SPI_WRITE signal is deactivated
and the SPI bit counter is set to 7 (it will count down as bits
are received).
When the CS goes low (active), the first SPI transfer will be
a command byte and the first bit indicates a write or read
command. The SPI_WRITE signal takes on the value of this
first bit, and the state machine enters the SPI_CMD_XFER
state, where the remaining bits of the command byte are
received. The last five bits of the command set the initial
value of the register pointer. After the command byte is
complete, the state machine advances to the SPI_BURST
state, which remains active until CS goes high (or the
MC33780 is reset).
In the SPI_BURST state, new SPI characters are read-
from, or written-to-and-read-from, MC33780 registers. If the
control register (or CRC polynomial, CRC seed, CRC length,
or spread spectrum control) is written, an ABORT request is
generated that will immediately stop any DBUS transfer that
was in progress (refer to the DBUS transfer state diagram). If
the DATA register low byte is written, a transmit FIFO push
operation is generated (see transmit FIFO state diagram). If
the DATA register low byte is accessed (read or written) and
there is at least one entry in the receive FIFO, a receive FIFO
pop operation is generated.
When a DBUS transfer results in both an R_FIFO_PUSH
and an X_FIFO_POP, the R_FIFO_PUSH is performed first
to avoid the possibility of the transmit FIFO from getting
ahead of the receive FIFO.
RSTB ACTIVE or CSB INACTIVE/
SPI_WRITE = 0;
SPI_BIT_PTR = 7;
SPI_IDLE
STATE TRANSITIONS OCCUR
ON POS EDGE OF SCLK
CSB ACTIVE/
SPI_WRITE= MOSI;
SPI_CMD_XFER
~LAST_SPI_BIT/
SPI_BIT_PTR = SPI_BIT_PTR-1;
LAST_SPI_BIT/
SPI_BIT_PTR = 7;
INIT_REG_PTR FROM CMD BITS[4:0]
LAST_SPI_BIT/
SPI_BURST
~LAST_SPI_BIT/
SPI_BIT_PTR = SPI_BIT_PTR-1;
SPI_BIT_PTR = 7;
REG_PTR = REG_PTR +1 (rolls over to 0 after 21);
if SPI_WRITE & REG_PTR = CTRL or POLY or SEED or LENGTH or SSCTRL then ABORT;
if SPI_WRITE & REG_PTR = DATA_L then X_FIFO_PUSH;
if R_FIFO_NOT_EMPTY & REG_PTR = DATA_L then R_FIFO_POP;
Figure 20. State Diagram of SPI Transfer
33780
24
Analog Integrated Circuit Device Data
Freescale Semiconductor