MC33780 Datasheet, PDF (23/37 Pages) Freescale Semiconductor, Inc – Dual DBUS Master with Differential Drive and Frequency Spreading

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
DBUS transmit buffer is empty. The INT output can only drive
the level on the terminal low. The internal pull-up current or
an external resistor to V_CC is used to pull this terminal high.
This is done so that other ICs can be connected to the
interrupt terminal on the MCU. If the DBUS IC or any of the
other ICs want to assert an interrupt to the MCU, they can do
so by pulling the terminal low. This is similar to a logical OR
of the outputs because this IC or any of the others can assert
the interrupt to the MCU. The operation of the Interrupt is
described in detail in the section titled Interrupt Generator.
RST
Asserting this terminal low will cause the part to reset,
forcing registers to a known state. The description for these
registers shows the bit values that will occur due to a reset.
All bus activity will be halted and not allowed to restart, and
no SPI activity will be recognized until the RST goes to a logic
high level.
CLOCK SELECT AND DIVIDER
There is an independent Clock Select and Divider for each
channel. These circuits are controlled by register writes to the
SPI and can select whether the Spread Spectrum Clock
(CLK_VCOn) is used for the bit clock or the unspread clock is
used. They also contain dividers that can be selected to
reduce the bit rate by integer ratios in the unspread mode
only.
RXFIFO
The RXFIFO is an automatic register set that allows up to
four responses to be stored without being transferred to the
MCU via the SPI. This is done so that data will not be lost
even if the MCU takes time to read the response data. When
the MCU reads a response from one of the DBUS registers,
the earliest response to be received is the one read. In other
words, the first in response will be the first out (FIFO). When
the RXFIFO becomes not empty and interrupts are enabled,
the MCU receives an interrupt via INT.
TXFIFO
The TXFIFO is an automatic register set that allows up to
four transmit data packets to be stored for future
transmission on the DBUS. This is done to prevent the
overwrite of transmit data if the transmission of the previous
data has not been completed. The oldest data in the registers
is the first to be sent when the DBUS is ready to send. In other
words, the first data put into the registers to be sent will be the
first out when the DBUS is available (FIFO). When the
TXFIFO becomes empty and interrupts are enabled, the
MCU receives an interrupt via INT.
CH0/CH1 ENABLE
The output of these signals control whether the DBUS can
drive power and signalling onto the bus. These are directly
controlled by bits written to the control registers.
Analog Integrated Circuit Device Data
Freescale Semiconductor
CH0/CH1 OUTPUTS
These signals control the physical layer drivers and
receive data from the physical layer receivers. The physical
layer will convert the 0 V to 5.0 V low power logic signals to
the higher voltage (up to 26.5 V) and drive (150 mA nominal)
levels necessary for the DBUS to be used. It also converts
the low current (0 mA to 11 mA typical) loading of the
response signal from the slave to logic voltage levels to allow
the response from the slaves to be received. These internal
signals are named DSIF, DSIS, and DSIR.
CRC GENERATORS
Each channel contains a CRC generator that adds a series
of bits to each of the transmitted data words sent out on the
DBUS. The CRC bits are created from the data pattern and
are used by the slave devices to determine if one or more of
the data bits sent was in error. The detailed operation and
control of this function is covered in the section entitled CRC
Generation /Checking.
CRC CHECK
This circuit checks the CRC bits that have been added to
the end of the response by the slave device. For a given
pattern of received data a new CRC is generated and
compared to the CRC bits received. If they do not match, a
bit is set in the status register indicating a CRC error for the
response. This bit is read back using the SPI during the same
SPI transaction that reads the response in order to keep them
associated with each other. The CRC bits are removed by the
IC and not seen by the MCU when reading the data registers.
Operation of the CRC Check is covered in the section entitled
CRC Generation /Checking.
SPI AND PROTOCOL ENGINE STATE MACHINES
Although the SPI clock and the DBUS input clock both
typically come from the same MCU system clock in an MCU
plus 33780 system, there is no guaranteed relationship
between these clocks, so the system was designed as if
these clocks were asynchronous. The FIFO architecture
eliminated most of the cases where these clocks need to
interact, and the remaining cases were designed with extra
care to prevent asynchronous problems.
Figure 19 explains the notation used in the subsequent
state diagrams. Entry to the IDLE state is asynchronous and
all other state transitions are synchronous. The note in the
upper right corner of the figure identifies which edge of which
clock or signal is used to synchronize state transitions. Each
arrow or arc has a condition that must be true before the
transition can take place. This condition can be the value of a
single signal or a more complex logic function. A slash (/)
indicates the end of the condition or equation, which must be
true for a transition to occur. The statement or statements
after the slash are executed during the transition to the next
state. These state diagrams are not a complete description of
the entire MC33780, they are intended to include just enough
relevant data to understand the operation of the state
machines and basic functions.
33780
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