MC33780 Datasheet, PDF (33/37 Pages) Freescale Semiconductor, Inc – Dual DBUS Master with Differential Drive and Frequency Spreading

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
DEV[1:0]–Spread Spectrum Frequency Deviation for
Channel n
These bits control the frequency deviation of the spread
spectrum signalling. DEV [1:0] is recommended to be
programmed to either 10 or 11 whenever the spread
spectrum is enabled. DEV = “00” (the default) and DEV = “01”
(typical 1000 nsec) are optionally available under application
usage.
DEV[1:0] = 10 = Deviation enabled.
DEV[1:0] = 11 = Deviation disabled.
The mode with deviation disabled may be used to achieve
fine control of the bit rate without frequency spreading.
DnOFFSETH and DnOFFSETL REGISTERS
These read/write registers control the spread spectrum
PLL offset value. There are four of these registers, two for
each DBUS channel. The bit assignments are shown in
Figure 34 and Figure 35.
SPI Data Bit
Read/Write
Reset
Bit 7
6
5
4
3
2
1
–
–
–
–
–
–
–
0
0
0
0
0
0
0
Figure 34. Dn Spread Spectrum Offset High Register Bit Assignments
0
OFFSETH8
0
SPI Data Bit
Read/Write
Reset
Bit 7
6
5
4
3
2
1
0
OFFSETL7 OFFSETL6 OFFSETL5 OFFSETL4 OFFSETL3 OFFSETL2 OFFSETL1 OFFSETL0
0
0
0
0
0
0
0
0
Figure 35. Dn Spread Spectrum Offset Low Register Bit Assignments
The OFFSETH[0] and OFFSETL[7:0] register bits control
the updating of the PLL loop center frequency. After reset or
when either of these registers is written to, the spread
spectrum PLL loop goes into fast acquisition mode for 64
cycles. After this, the PLL switches to slow acquisition mode.
The default value of 0 0000 0000 sets the PLL to the
minimum data rate available.
DnSSUD Registers
These read-only registers reflect the spread spectrum PLL
loop 6-bit update count. There are two of these registers, one
for each DBUS channel. The bit assignments are shown in
Figure 36 and Figure 37.
D0SSUD also contains an ID bit in D0SSUD[2] which is
hardwired to logic 1. This bit is a 1 regardless of the state of
the spread-spectrum control bits in DOSSCTRL.
SPI Data Bit
Read
Reset
Bit 7
0
0
6
5
4
3
2
1
0
SSUD5 SSUD4 SSUD3
ID
SSUD1
0
1
0
0
1
0
Figure 36. D0 Spread Spectrum Up/Down Register Bit Assignments
0
SSUD0
0
SPI Data Bit
Read
Reset
Bit 7
0
0
6
5
4
3
2
1
0
0
SSUD5 SSUD4 SSUD3 SSUD2 SSUD1 SSUD0
0
1
0
0
0
0
0
Figure 37. Dn Spread Spectrum Up/Down Register Bit Assignments
The SSUD[5:0] value reflects the current state of the PLL
loop up/down counter. This 6-bit value is the control input to
the Center Frequency DAC of Figure 12. This 6-bit value is
normalized to the center frequency of the PLL.A write to the
register will be ignored. The 6-bit SSUD value will be latched
whenever CS transitions low so that the value of SSUD will
not change during an SPI command.
The default value of 10 0000 puts the VCO at the center of
its range to minimize the PLL acquisition time.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33780
33