MC33780 Datasheet, PDF (6/37 Pages) Freescale Semiconductor, Inc – Dual DBUS Master with Differential Drive and Frequency Spreading

STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 4.75 V ≤ V_CC ≤ 5.25 V, 9.0 V ≤ V_SUP ≤ 25 V,-40°C ≤ T_A ≤ 85°C unless otherwise
noted. Voltages relative to GND unless otherwise noted. Typical values noted reflect the approximate parameter means at
T_A = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Vmid, (DnH + DnL)/2 (Voltage Halfway Between Bus High Side and
Bus Low Side)
V_mid
V_SUP/2 -
V_SUP/ 2
V_SUP /
V
1.0
2 +1.0
V_CM Peak-to-Peak, Vmid (Signal High) - Vmid (Signal Low) ⁽⁵⁾
V_CMpp
–
0.3
–
V
Output High-Side (DnH) Idle Driver Current Limit (DnL open)
Source: DnH = 0 V
Sink: DnH = V_SUP
I_{ICL (HIGH)}
mA
-400
–
-200
100
–
–
Output Low-Side (DnL) Idle Driver Current Limit (DnH open)
Source: DnL = 0 V
Sink: DnL = V_SUP
I_{ICL (LOW)}
–
mA
–
-100
200
–
400
Output High-Side (DnH) Signal Driver Overcurrent Shutdown
Source: Signal High, Signal Low
Sink: Signal High, Signal Low
I_{SCL (HIGH)}
-100
–
30
–
mA
-30
100
Output Low-Side (DnL) Signal Driver Overcurrent Shutdown
Source: Signal High, Signal Low
Sink: Signal High, Signal Low
I_{SCL (LOW)}
-100
–
30
–
mA
-30
100
Disabled High-Side (DnH) Bus Leakage (DnL open)
DnH = 0 V
DnH = V_SUP
Disabled Low-Side (DnL) Bus Leakage (DnH open)
DnL = 0 V
DnL = V_SUP
BUS RECEIVER (D0H, D0L, D1H, D1L)
I_LK(HIGH)
mA
-1.0
-0.18
1.0
-1.0
0.25
1.0
I_LK(LOW)
mA
-1.0
-0.4
1.0
-1.0
0.08
1.0
Comparator Trip Point
Notes
5. Not measured in production.
COMP(TRIP)
5.0
6.0
7.0
mA
33780
6
Analog Integrated Circuit Device Data
Freescale Semiconductor