MC33780 Datasheet, PDF (14/37 Pages) Freescale Semiconductor, Inc – Dual DBUS Master with Differential Drive and Frequency Spreading

FUNCTIONAL DESCRIPTIONS
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
the DBUS physical layer as shown in Figure 5. They also
provide power to the slave modules during the DBUS idle
time. The output of DnL should have a bypass capacitor of
4.7 nF to ground.
HIGH-SIDE BUS (DnH)
There are two independent HIGH-SIDE outputs, D0H and
D1H They comprise the high-side differential output signal of
the DBUS physical layer. They also provide power to the
slave modules during the DBUS idle time. See Figure 5. The
output of DnL should have a bypass capacitor of 4.7 nF to
ground.
POSITIVE SUPPLY FOR BUS OUTPUT (VSUP)
This 9.0 V to 25 V power supply is used to provide power
to the slave devices attached to the DBUS. During the bus
idle time, the storage capacitors in the slave modules are
charged up to maintain a regulated supply to the slave
device.
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
SPI and
Registers
DBUS
Driver /Receiver
Interrupt
Generator
Protocol
Engine
Figure 9. Block Illustration
The 33780 is controlled by an MCU through an SPI
interface. It handles the digital and physical layer portions of
a DBUS master node. Two separate DBUS channels are
included, each capable of interfacing to up to 15 DBUS slave
devices (nodes). The physical layer uses a two-wire bus with
analog wave-shaped voltage and current signals. Refer to
Figure 1.
Major subsystems include the following:
• SPI interface to an MCU
• A register pointer block
• Two channels of DBUS protocol state logic
• CRC block for each channel
• Control and status registers
• 4-level FIFOs on each transmit and receive buffer
SPI AND REGISTERS
This block contains the SPI interface logic and the control
and response registers that are written to and read from the
SPI interface.
The IC is an SPI slave-type device, so MOSI (Master-Out-
Slave-In) is an input and MISO (Master-In-Slave-Out) is an
output. CS and SCLK are also inputs.
33780
14
The SPI port will handle byte and multi-byte transfers. It
addresses 22 registers. The 33780 combines the functions of
both the 68HC55 (DSID) and the 33790 (DSIP). The 33780
uses the eight control registers defined in the DSID, and the
remaining registers are needed for the additional modes of
operation in the 33780. The organization of the registers is
described in the section entitled Register and Bit
Descriptions.
INTERRUPT GENERATOR
This circuit accepts unmasked interrupt inputs for data
flow. It drives an open-drain output that allows the output to
be OR connected with other open-drain outputs so that this
IC or any of the others can assert an interrupt. An unmasked
interrupt will cause the INT to pull down the output. Interrupts
can be generated by two circumstances: (1) a Transmit FIFO
register becoming empty, or (2) the Receive FIFO becoming
not empty. Both of these events occur at the end of a DBUS
transaction. Either of these two events will generate an
interrupt when enabled by setting bits in the DnCTRL
registers.
Similarly, the interrupt signal can be cleared in two ways:
(1) the Transmit FIFO becomes not empty, or (2) the Receive
FIFO becomes empty. Both of these events are checked at
the end of an SPI word (either with CS rising or with the rising
edge of SCLK of a new data byte in an SPI burst).
Analog Integrated Circuit Device Data
Freescale Semiconductor