MC33780 Datasheet, PDF (29/37 Pages) Freescale Semiconductor, Inc – Dual DBUS Master with Differential Drive and Frequency Spreading

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
DnL REGISTERS
These are read/write registers. There are two of these
registers, one for each of the buses. When written to, the data
is the low byte of a 16-bit command. When read, it is the
low byte of a 16-bit return on the DBUS. Writing to this
register initiates a DBUS transaction. The bit assignments
are shown in Figure 26
.
SPI Data Bit
Bit 7
6
5
4
3
2
1
0
Read / Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
0
0
0
0
0
0
0
0
Figure 26. DnL Data Register Bit Assignments
D01STAT REGISTER
This is a read-only register. This register covers the status
of DBUS 0 and 1. The values are latched when CS is
asserted low. Any changes of the status that these bits detect
will not be transferred to the register until CS is de-
asserted. This is done to ensure that partial updates will not
occur. The bit assignments are shown in Figure 27
.
SPI Data Bit
Bit 7
6
5
4
3
2
1
0
Read
Reset
ER1
TFE1
TFNF1
RFNE1
ER0
TFE0
TFNF0
RFNE0
0
1
1
0
0
1
1
0
Figure 27. Channel 1 and 2 Status Register Bit Assignments
ERn–CRC Error Bit for Channel n
• 0 = CRC value for the data in the read buffer was correct
and no overcurrent condition exists.
• 1 = CRC value for the data in the read buffer was not
correct (data not valid) or that an overcurrent event has
occurred.
CRC errors are associated with each data value in the
receive FIFO, so each FIFO entry has a bit to indicate
whether the data in that stage of the FIFO was received
correctly.
Whenever a received data value is available in the DnH
and DnL registers, the associated CRC error status is
available at ERn in the D01STAT register. When a new data
value becomes available owing to a pop (read) of a previous
value, the ERn status flag reflects the CRC status of the new
data value. There is no separate interrupt associated with
ERn because it is always associated with the RFNEn status
flag.
TFEn–Transmit FIFO Empty Bit for Channel n
• 0 = Transmit FIFO not empty.
• 1 = Transmit FIFO empty.
When the transmit FIFO is empty, four consecutive write
bursts may be used to fill the FIFO without checking the flags
between writes. INT will be asserted on the transmit FIFO
empty condition if TIEn is set. INT will be de-asserted when
TIEn is cleared or a byte is written to DnL.
TFNFn–Transmit FIFO Not Full Bit for Channel n
• 0 = Transmit FIFO full; no more room for additional
data.
• 1 = Transmit FIFO not full; there is room for more data
in the transmit FIFO.
There is no interrupt associated with the transmit FIFO not
full condition. When the conclusion of a transfer frame would
cause both TFNF and RFNE to become set, RFNE becomes
set but TFNF is not set until one clock cycle later. When the
transmit FIFO is full, attempts to write more data into the
FIFO are ignored.
RFNEn–Receive FIFO Not Empty Bit for Channel n
• 0 = No new data ready.
• 1 = One or more data entries in the receive FIFO; data
is available to be read.
It is not possible to overflow the receive FIFO because it is
not possible to get more than four transmit messages into the
system at a time. When there is any data in the receive FIFO,
a write to the transmit buffer also pops data from the receive
FIFO. If RIEn is set, INT will be asserted if this bit is set and
data becomes available in the receive buffers.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33780
29