MC9328MXL Datasheet, PDF (76/84 Pages) Freescale Semiconductor, Inc – i.MX Integrated Portable System Processor

Specifications
1
VSYNC
HSYNC
2
PIXCLK
7
6
5
DATA[7:0]
Valid Data
Valid Data
Valid Data
3
4
Figure 60. Sensor Output Data on Pixel Clock Rising Edge
CSI Latches Data on Pixel Clock Falling Edge
Ref No.
1
2
3
4
5
6
7
Table 31. Gated Clock Mode Timing Parameters
Parameter
Min
Max
csi_vsync to csi_hsync
180
–
csi_hsync to csi_pixclk
1
–
csi_d setup time
1
–
csi_d hold time
1
–
csi_pixclk high time
10.42
–
csi_pixclk low time
10.42
–
csi_pixclk frequency
0
48
Unit
ns
ns
ns
ns
ns
ns
MHz
The limitation on pixel clock rise time / fall time are not specified. It should be calculated from the hold time and
setup time, according to:
Rising-edge latch data
max rise time allowed = (positive duty cycle - hold time)
max fall time allowed = (negative duty cycle - setup time)
In most of case, duty cycle is 50 / 50, therefore
max rise time = (period / 2 - hold time)
max fall time = (period / 2 - setup time)
For example: Given pixel clock period = 10ns, duty cycle = 50 / 50, hold time = 1ns, setup time = 1ns.
positive duty cycle = 10 / 2 = 5ns
=> max rise time allowed = 5 - 1 = 4ns
MC9328MXL Advance Information, Rev. 5
76
Freescale Semiconductor