MC9328MXL Datasheet, PDF (6/84 Pages) Freescale Semiconductor, Inc – i.MX Integrated Portable System Processor

Signals and Connections
2 Signals and Connections
Table 3 identifies and describes the MC9328MXL signals that are assigned to package pins. The signals are
grouped by the internal module that they are connected to.
Table 3. MC9328MXL Signal Descriptions
Signal Name
Function/Notes
A[24:0]
D[31:0]
EB0
EB1
EB2
EB3
OE
CS [5:0]
ECB
LBA
BCLK (burst clock)
RW
DTACK
BOOT [3:0]
SDBA [4:0]
SDIBA [3:0]
MA [11:10]
MA [9:0]
DQM [3:0]
CSD0
External Bus/Chip-Select (EIM)
Address bus signals
Data bus signals
MSB Byte Strobe—Active low external enable byte signal that controls D [31:24].
Byte Strobe—Active low external enable byte signal that controls D [23:16].
Byte Strobe—Active low external enable byte signal that controls D [15:8].
LSB Byte Strobe—Active low external enable byte signal that controls D [7:0].
Memory Output Enable—Active low output enables external data bus.
Chip-Select—The chip-select signals CS [3:2] are multiplexed with CSD [1:0] and are selected by the
Function Multiplexing Control Register (FMCR). By default CSD [1:0] is selected.
Active low input signal sent by a flash device to the EIM whenever the flash device must terminate an
on-going burst sequence and initiate a new (long first access) burst sequence.
Active low signal sent by a flash device causing the external burst device to latch the starting burst
address.
Clock signal sent to external synchronous memories (such as burst flash) during burst mode.
RW signal—Indicates whether external access is a read (high) or write (low) cycle. Used as a WE
input signal by external DRAM.
DTACK signal—The external input data acknowledge signal. When using the external DTACK signal
as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is
not terminated by the external DTACK signal after 1022 clock counts have elapsed.
Bootstrap
System Boot Mode Select—The operational system boot mode of the MC9328MXL upon system
reset is determined by the settings of these pins.
SDRAM Controller
SDRAM/SyncFlash non-interleave mode bank address multiplexed with address signals A [15:11].
These signals are logically equivalent to core address p_addr [25:21] in SDRAM/SyncFlash cycles.
SDRAM/SyncFlash interleave addressing mode bank address multiplexed with address signals A
[19:16]. These signals are logically equivalent to core address p_addr [12:9] in SDRAM/SyncFlash
cycles.
SDRAM address signals
SDRAM address signals which are multiplexed with address signals A [10:1]. MA [9:0] are selected
on SDRAM/SyncFlash cycles.
SDRAM data enable
SDRAM/SyncFlash Chip-select signal which is multiplexed with the CS2 signal. These two signals
are selectable by programming the system control register.
MC9328MXL Advance Information, Rev. 5
6
Freescale Semiconductor