MC9328MXL Datasheet, PDF (61/84 Pages) Freescale Semiconductor, Inc – i.MX Integrated Portable System Processor

Specifications
Active which sets up the status register read. The bank and row addresses are driven during this command.
The third command of the triplet is Read. Bank and column addresses are driven on the address bus during
this command. Data is returned from memory on the low order 8 data bits following the CAS latency.
1
SDCLK
CS
2
3S
3
3S
RAS
CAS
WE
3H
3S
3H
3H
3S
3H
ADDR
4S 4H
ROW/BA
COL/BA
DQ
DQM
8
3S
5
6
Data
7
3H
Note: CKE is high during the read/write cycle.
Figure 48. SDRAM/SyncFlash Read Cycle Timing Diagram
Table 23. SDRAM Timing Parameter Table
1.8V ± 0.10V
3.0V ± 0.30V
Ref
No.
Parameter
Unit
Minimum Maximum Minimum Maximum
1 SDRAM clock high-level width
2 SDRAM clock low-level width
3 SDRAM clock cycle time
3S CS, RAS, CAS, WE, DQM setup time
2.67
–
4
–
ns
6
–
4
–
ns
11.4
–
10
–
ns
3.42
–
3
–
ns
MC9328MXL Advance Information, Rev. 5
Freescale Semiconductor
61