MC9328MXL Datasheet, PDF (74/84 Pages) Freescale Semiconductor, Inc – i.MX Integrated Portable System Processor

Specifications
Table 30. SSI (Port B Alternate Function) Timing Parameter Table (Continued)
Ref
No.
Parameter
1.8V ± 0.10V
3.0V ± 0.30V
Unit
Minimum Maximum Minimum Maximum
Synchronous Internal Clock Operation (Port B Alternate Function²)
31 SRXD setup before STCK falling
32 SRXD hold after STCK falling
18.81
–
16.5
–
ns
0
–
0
–
ns
Synchronous External Clock Operation (Port B Alternate Function²)
33 SRXD setup before STCK falling
1.14
–
1.0
–
ns
34 SRXD hold after STCK falling
0
–
0
–
ns
1. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a
non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been
inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync
STFS/SRFS shown in the tables and in the figures.
2. There are 2 set of I/O signals for the SSI module. They are from Port C primary function (pad 257 to pad
261) and Port B alternate function (pad 283 to pad 288). When SSI signals are configured as outputs, they
can be viewed both at Port C primary function and Port B alternate function. When SSI signals are
configured as inputs, the SSI module selects the input based on FMCR register bits in the Clock controller
module (CRM). By default, the input are selected from Port C primary function.
3. bl = bit length; wl = word length.
MC9328MXL Advance Information, Rev. 5
74
Freescale Semiconductor