MC9328MXL Datasheet, PDF (47/84 Pages) Freescale Semiconductor, Inc – i.MX Integrated Portable System Processor

SS (input)
6
7
SCLK, MOSI, MISO
Specifications
Figure 35. Slave SPI Timing Diagram FIFO Advanced by SS Rising Edge
Table 15. Timing Parameter Table for Figure 31 through Figure 35
1.8V ± 0.10V
3.0V ± 0.30V
Ref
No.
Parameter
Unit
Minimum Maximum Minimum Maximum
1 SPI_RDY to SS output low
2T ¹
–
2T¹
–
ns
2 SS output low to first SCLK
3 • Tsclk ²
–
3 • Tsclk²
–
ns
edge
3 Last SCLK edge to SS output 2 • Tsclk
–
2 • Tsclk
–
ns
high
4 SS output high to SPI_RDY
0
–
0
–
ns
low
5 SS output pulse width
Tsclk +
–
Tsclk +
–
ns
WAIT ³
WAIT³
6 SS input low to first SCLK
T
–
T
–
ns
edge
7 SS input pulse width
T
–
T
–
ns
1. T = CSPI system clock period (PERCLK2).
2. Tsclk = Period of SCLK.
3. WAIT = Number of bit clocks (SCLK) or 32.768 kHz clocks per Sample Period Control Register.
3.11 LCD Controller
This section includes timing diagrams for the LCD controller. For detailed timing diagrams of the LCD
controller with various display configurations, refer to the LCD controller chapter of the MC9328MXL
Reference Manual.
LSCLK
LD[15:0]
1
Figure 36. SCLK to LD Timing Diagram
MC9328MXL Advance Information, Rev. 5
Freescale Semiconductor
47