MC9328MXL Datasheet, PDF (49/84 Pages) Freescale Semiconductor, Inc – i.MX Integrated Portable System Processor

Table 17. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing (Continued)
Specifications
Symbol
Description
Minimum
Corresponding Register Value
Unit
T7
End of OE to beginning of HSYN
1
HWAIT1+1
Ts
T8
SCLK to valid LD data
-3
3
ns
T9
End of HSYN idle2 to VSYN edge
2
(for non-display region)
2
Ts
T9
End of HSYN idle2 to VSYN edge
1
(for Display region)
1
Ts
T10
VSYN to OE active (Sharp = 0)
1
when VWAIT2 = 0
1
Ts
T10
VSYN to OE active (Sharp = 1)
2
when VWAIT2 = 0
2
Ts
Note:
•
•
•
•
•
•
Ts is the SCLK period which equals LCDC_CLK / (PCD + 1). Normally LCDC_CLK = 15ns.
VSYN, HSYN and OE can be programmed as active high or active low. In Figure 37, all 3 signals are active low.
The polarity of SCLK and LD[15:0] can also be programmed.
SCLK can be programmed to be deactivated during the VSYN pulse or the OE deasserted period. In Figure 37, SCLK
is always active.
For T9 non-display region, VSYN is non-active. It is used as an reference.
XMAX is defined in pixels.
MC9328MXL Advance Information, Rev. 5
Freescale Semiconductor
49