MC9328MXL Datasheet, PDF (50/84 Pages) Freescale Semiconductor, Inc – i.MX Integrated Portable System Processor

Specifications
3.12 Multimedia Card/Secure Digital Host Controller
The DMA interface block controls all data routing between the external data bus (DMA access), internal
MMC/SD module data bus, and internal system FIFO access through a dedicated state machine that
monitors the status of FIFO content (empty or full), FIFO address, and byte/block counters for the
MMC/SD module (inner system) and the application (user programming).
Bus Clock
CMD_DAT Input
3a
4a
5a
Valid Data
CMD_DAT Output
12
3b
4b
7
Valid Data
6a
5b
Valid Data
Valid Data
6b
Figure 38. Chip-Select Read Cycle Timing Diagram
Table 18. SDHC Bus Timing Parameter Table
1.8V ± 0.10V
3.0 ± 0.30V
Ref
No.
Parameter
Unit
Minimum Maximum Minimum Maximum
1 CLK frequency at Data transfer Mode
0
25/5
0
(PP)¹â€”10/30 cards
2 CLK frequency at Identification Mode²
0
400
0
3a Clock high time¹â€”10/30 cards
6/33
–
10/50
3b Clock low time¹â€”10/30 cards
4a Clock fall time¹â€”10/30 cards
15/75
–
–
10/50
(5.00)³
10/50
–
4b Clock rise time¹â€”10/30 cards
–
14/67
–
(6.67)³
5a Input hold time³â€”10/30 cards
5.7/5.7
–
5/5
5b Input setup time³â€”10/30 cards
5.7/5.7
–
5/5
6a Output hold time³â€”10/30 cards
5.7/5.7
–
5/5
6b Output setup time³â€”10/30 cards
5.7/5.7
–
5/5
7 Output delay time³
0
16
0
1. C_L ≤ 100 pF / 250 pF (10/30 cards)
2. C_L ≤ 250 pF (21 cards)
3. C_L ≤ 25 pF (1 card)
MC9328MXL Advance Information, Rev. 5
50
25/5
MHz
400
kHz
–
ns
–
ns
10/50
ns
10/50
ns
–
ns
–
ns
–
ns
–
ns
14
ns
Freescale Semiconductor