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MC9328MXL Datasheet, PDF (16/84 Pages) Freescale Semiconductor, Inc – i.MX Integrated Portable System Processor | |||
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Specifications
3.7 DPLL Timing Specifications
Parameters of the DPLL are given in Table 10. In this table, Tref is a reference clock period after the
pre-divider and Tdck is the output double clock period.
Table 10. DPLL Specifications
Parameter
Test Conditions
Minimum Typical Maximum Unit
Reference clock freq range
Vcc = 1.8V
Pre-divider output clock
freq range
Vcc = 1.8V
Double clock freq range
Vcc = 1.8V
Pre-divider factor (PD)
â
Total multiplication factor (MF) Includes both integer
and fractional parts
MF integer part
â
MF numerator
Should be less than the
denominator
MF denominator
â
Pre-multiplier lock-in time
â
Freq lock-in time after
full reset
FOL mode for non-integer MF
(does not include pre-multi lock-in
time)
Freq lock-in time after
partial reset
FOL mode for non-integer MF
(does not include pre-multi lock-in
time)
Phase lock-in time after
full reset
FPL mode and integer MF (does
not include pre-multi lock-in time)
Phase lock-in time after
partial reset
FPL mode and integer MF (does
not include pre-multi lock-in time)
Freq jitter (p-p)
â
Phase jitter (p-p)
Integer MF, FPL mode, Vcc=1.8V
Power supply voltage
Power dissipation
â
FOL mode, integer MF,
fdck = 200 MHz, Vcc = 1.8V
5
â
100
MHz
5
â
30
MHz
80
â
220
MHz
1
â
16
â
5
â
15
â
5
â
15
â
0
â
1022
â
1
â
1023
â
â
â
312.5
µsec
250
280
300
Tref
(56 µs)
220
250
270
Tref
(50 µs)
300
350
400
Tref
(70 µs)
270
320
370
Tref
(64 µs)
â
0.005
0.01
2â¢Tdck
(0.01%)
â
1.0
1.5
ns
(10%)
1.7
â
2.5
V
â
â
4
mW
MC9328MXL Advance Information, Rev. 5
16
Freescale Semiconductor
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