MC9328MXL Datasheet, PDF (21/84 Pages) Freescale Semiconductor, Inc – i.MX Integrated Portable System Processor

3.9.1 DTACK Signal Description
Specifications
The DTACK signal is the external input data acknowledge signal. When using the external DTACK signal
as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not
terminated by the external DTACK signal after 1022 HCLK counts have elapsed. Only CS5 group is
designed to support DTACK signal function when using the external DTACK signal for data
acknowledgement.
3.9.2 DTACK Signal Timing
Figure 6 shows the access cycle timing used by chip-select 5. The signal values and units of measure for
this figure are found in Table 13.
HCLK
CS5
RW
1
OE
EXT_DTACK
2
INT_DTACK
3
5
4
Figure 6. DTACK Timing, WSC=111111, DTACK_sel=0
Table 13. Access Cycle Timing Parameters
Ref
No.
Characteristic
1.8V ± 0.10V
Min
Max
3.0V ± 0.30V
Unit
Min
Max
1
CS5 asserted to OE asserted
–
T
–
T
ns
2
External DTACK input setup from CS5
asserted
0
–
0
–
ns
3
CS5 pulse width
3T
–
3T
–
ns
4
External DTACK input hold after CS5 is
negated
0
1.5T
0
1.5T
ns
5
OE negated after CS5 is negated
0
4.5
0
4
ns
Note:
1. n is the number of wait states in the current memory access cycle. The max n is 1022.
2. T is the system clock period (system clock is 96 MHz).
3. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.
MC9328MXL Advance Information, Rev. 5
Freescale Semiconductor
21