K20P144M120SF3 Datasheet, PDF (70/80 Pages) Freescale Semiconductor, Inc – K20 Sub-Family Data Sheet

Pinout
8.1 K20 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
144 144 Pin Name Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
LQF MAP
P BGA
— L5 RTC_WAKE RTC_WAKE RTC_WAKE
UP_B
UP_B
UP_B
— M5 NC
NC
NC
— A10 NC
NC
NC
— B10 NC
NC
NC
— C10 NC
NC
NC
1 D3 PTE0
ADC1_SE4 ADC1_SE4 PTE0
a
a
SPI1_PCS1 UART1_TX SDHC0_D1
I2C1_SDA RTC_CLKO
UT
2 D2 PTE1/
ADC1_SE5 ADC1_SE5 PTE1/
SPI1_SOUT UART1_RX SDHC0_D0
LLWU_P0 a
a
LLWU_P0
I2C1_SCL SPI1_SIN
3 D1 PTE2/
ADC1_SE6 ADC1_SE6 PTE2/
SPI1_SCK UART1_CT SDHC0_DC
LLWU_P1 a
a
LLWU_P1
S_b
LK
4 E4 PTE3
ADC1_SE7 ADC1_SE7 PTE3
a
a
SPI1_SIN UART1_RT SDHC0_CM
S_b
D
SPI1_SOUT
5 E5 VDD
VDD
VDD
6 F6 VSS
VSS
VSS
7 E3 PTE4/
DISABLED
LLWU_P2
PTE4/
SPI1_PCS0 UART3_TX SDHC0_D3
LLWU_P2
8 E2 PTE5
DISABLED
PTE5
SPI1_PCS2 UART3_RX SDHC0_D2
FTM3_CH0
9 E1 PTE6
DISABLED
PTE6
SPI1_PCS3 UART3_CT I2S0_MCLK
S_b
FTM3_CH1 USB_SOF_
OUT
10 F4 PTE7
DISABLED
PTE7
UART3_RT I2S0_RXD0
S_b
FTM3_CH2
11 F3 PTE8
ADC2_SE1 ADC2_SE1 PTE8
6
6
I2S0_RXD1 UART5_TX I2S0_RX_F
S
FTM3_CH3
12 F2 PTE9
ADC2_SE1 ADC2_SE1 PTE9
7
7
I2S0_TXD1 UART5_RX I2S0_RX_B
CLK
FTM3_CH4
13 F1 PTE10
DISABLED
PTE10
UART5_CT I2S0_TXD0
S_b
FTM3_CH5
14 G4 PTE11
ADC3_SE1 ADC3_SE1 PTE11
6
6
UART5_RT I2S0_TX_F
S_b
S
FTM3_CH6
15 G3 PTE12
ADC3_SE1 ADC3_SE1 PTE12
7
7
I2S0_TX_B
CLK
FTM3_CH7
16 E6 VDD
VDD
VDD
17 F7 VSS
VSS
VSS
18 H3 VSS
VSS
VSS
19 H1 USB0_DP USB0_DP USB0_DP
20 H2 USB0_DM USB0_DM USB0_DM
21 G1 VOUT33 VOUT33 VOUT33
K20 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
70
Preliminary
Freescale Semiconductor, Inc.