K20P144M120SF3 Datasheet, PDF (51/80 Pages) Freescale Semiconductor, Inc – K20 Sub-Family Data Sheet

Peripheral operating requirements and behaviors
Table 30. 16-bit ADC with PGA characteristics (continued)
Symbol
E_IL
Description
Input leakage
error
Conditions
All modes
V_PP,DIFF
Maximum
differential input
signal swing
SNR
Signal-to-noise
ratio
THD
Total harmonic
distortion
• Gain=1
• Gain=64
• Gain=1
• Gain=64
SFDR
Spurious free
dynamic range
• Gain=1
• Gain=64
ENOB
Effective number
of bits
• Gain=1, Average=4
• Gain=1, Average=8
• Gain=64, Average=4
• Gain=64, Average=8
• Gain=1, Average=32
• Gain=2, Average=32
• Gain=4, Average=32
• Gain=8, Average=32
• Gain=16, Average=32
• Gain=32, Average=32
• Gain=64, Average=32
Min.
Typ.¹
I_In × R_AS
Max.
Unit
Notes
mV
I_In = leakage
current
(refer to the
MCU's voltage
and current
operating
ratings)
V
6
where V_X = V_REFPGA × 0.583
80
90
—
52
66
—
85
100
—
49
95
—
85
105
—
53
88
—
11.6
13.4
—
TBD
12.7
—
7.2
9.6
—
TBD
8.7
—
12.8
14.5
—
11.0
14.3
—
7.9
13.8
—
7.3
13.1
—
6.8
12.5
—
6.8
11.5
—
7.5
10.6
—
dB
16-bit
dB
differential
mode,
Average=32
dB
16-bit
dB
differential
mode,
Average=32,
f_in=100Hz
dB
16-bit
dB
differential
mode,
Average=32,
f_in=100Hz
bits
16-bit
bits
differential
mode,f_in=100H
bits
z
bits
bits
bits
bits
bits
bits
bits
bits
SINAD
Signal-to-noise
plus distortion
ratio
See ENOB
6.02 × ENOB + 1.76
dB
1. Typical values assume V_DDA =3.0V, Temp=25°C, f_ADCK=6MHz unless otherwise stated.
2. This current is a PGA module adder, in addition to and ADC conversion currents.
3. Between IN+ and IN-. The PGA draws a DC current from the input terminals. The magnitude of the DC current is a strong
function of input common mode voltage (V_CM) and the PGA gain.
4. _{Gain = 2}^PGAG
5. After changing the PGA gain setting, a minimum of 2 ADC+PGA conversions should be ignored.
K20 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
51