K20P144M120SF3 Datasheet, PDF (66/80 Pages) Freescale Semiconductor, Inc – K20 Sub-Family Data Sheet

Peripheral operating requirements and behaviors
SDHC_CLK
SD3
SD2
SD1
SD6
Output SDHC_CMD
Output SDHC_DAT[3:0]
Input SDHC_CMD
SD7
SD8
Input SDHC_DAT[3:0]
Figure 30. SDHC timing
6.8.11 I2S/SAI Switching Specifications
This section provides the AC timing for the I2S/SAI module in master mode (clocks are
driven) and slave mode (clocks are input). All timing is given for noninverted serial clock
polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame sync (TCR4[FSP]
is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame sync have been
inverted, all the timing remains valid by inverting the bit clock signal (BCLK) and/or the
frame sync (FS) signal shown in the following figures.
Table 46. I2S/SAI master mode timing
Num.
S1
S2
S3
S4
S5
S6
S7
S8
S9
Characteristic
Operating voltage
I2S_MCLK cycle time¹
I2S_MCLK pulse width high/low
I2S_TX_BCLK cycle time (output)¹
I2S_RX_BCLK cycle time (output)¹
I2S_TX_BCLK pulse width high/low
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
I2S_TX_BCLK to I2S_TXD valid
I2S_TX_BCLK to I2S_TXD invalid
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
Min.
1.71
40
45%
80
160
45%
—
Max.
3.6
55%
—
—
55%
15
Unit
V
ns
MCLK period
ns
BCLK period
ns
0
—
ns
—
15
ns
0
—
ns
25
—
ns
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
66
Preliminary
Freescale Semiconductor, Inc.