K20P144M120SF3 Datasheet, PDF (52/80 Pages) Freescale Semiconductor, Inc – K20 Sub-Family Data Sheet

Peripheral operating requirements and behaviors
6. Limit the input signal swing so that the PGA does not saturate during operation. Input signal swing is dependent on the
PGA reference voltage and gain setting.
6.6.2 CMP and 6-bit DAC electrical specifications
Table 31. Comparator and 6-bit DAC electrical specifications
Symbol Description
Min.
Typ.
Max.
Unit
V_DD
Supply voltage
1.71
—
3.6
V
I_DDHS Supply current, High-speed mode (EN=1, PMODE=1)
—
—
200
μA
I_DDLS
Supply current, low-speed mode (EN=1, PMODE=0)
—
—
20
μA
V_AIN
Analog input voltage
V_SS – 0.3
—
V_DD
V
V_AIO
Analog input offset voltage
—
—
20
mV
V_H
Analog comparator hysteresis¹
• CR0[HYSTCTR] = 00
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
—
5
—
mV
—
10
—
mV
—
20
—
mV
—
30
—
mV
V_CMPOh
V_CMPOl
t_DHS
t_DLS
I_DAC6b
INL
DNL
Output high
Output low
Propagation delay, high-speed mode (EN=1,
PMODE=1)
Propagation delay, low-speed mode (EN=1,
PMODE=0)
Analog comparator initialization delay²
6-bit DAC current adder (enabled)
6-bit DAC integral non-linearity
6-bit DAC differential non-linearity
V_DD – 0.5
—
—
—
20
50
80
250
—
—
—
7
–0.5
—
–0.3
—
—
V
0.5
V
200
ns
600
ns
40
μs
—
μA
0.5
LSB³
0.3
LSB
1. Typical hysteresis is measured with input voltage range limited to 0.6 to V_DD-0.6V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN,
VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level.
3. 1 LSB = V_reference/64
K20 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
52
Preliminary
Freescale Semiconductor, Inc.