K20P144M120SF3 Datasheet, PDF (67/80 Pages) Freescale Semiconductor, Inc – K20 Sub-Family Data Sheet

Peripheral operating requirements and behaviors
Table 46. I2S/SAI master mode timing (continued)
Num.
Characteristic
Min.
Max.
Unit
S10
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0
—
ns
S11
I2S_TX_FS input assertion to I2S_TXD output valid^{2 —}
21
ns
1. This parameter is limited in VLPx modes.
2. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
I2S_MCLK (output)
I2S_TX_BCLK/
I2S_RX_BCLK (output)
I2S_TX_FS/
I2S_RX_FS (output)
I2S_TX_FS/
I2S_RX_FS (input)
I2S_TXD
I2S_RXD
S1
S2
S2
S3
S4
S4
S5
S9
S7
S9
S10
S7
S8
S6
S10
S8
Figure 31. I2S/SAI timing — master modes
Num.
S11
S12
S13
S14
S15
S16
S17
S18
S19
Table 47. I2S/SAI slave mode timing
Characteristic
Operating voltage
I2S_RX_BCLK cycle time (input)
I2S_TX_BCLK cycle time (input)
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid
I2S_RXD setup before I2S_RX_BCLK
I2S_RXD hold after I2S_RX_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid¹
Min.
1.71
80
160
45%
10
2
—
0
10
2
—
Max.
3.6
—
—
55%
—
—
29
—
—
—
21
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
Unit
V
ns
MCLK period
ns
ns
ns
ns
ns
ns
ns
K20 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
67