K20P144M120SF3 Datasheet, PDF (26/80 Pages) Freescale Semiconductor, Inc – K20 Sub-Family Data Sheet

Peripheral operating requirements and behaviors
Table 13. JTAG voltage range electricals (continued)
Symbol
J4
J5
J6
J7
J8
J9
J10
J11
Description
TCLK rise and fall times
TMS input data setup time to TCLK rise
• JTAG
• CJTAG
TDI input data setup time to TCLK rise
TMS input data hold time after TCLK rise
• JTAG
• CJTAG
TDI input data hold time after TCLK rise
TCLK low to TMS data valid
• JTAG
• CJTAG
TCLK low to TDO data valid
Output data hold/invalid time after clock edge¹
Min.
Max.
Unit
—
1
ns
53
—
ns
112
8
—
ns
3.4
—
ns
3.4
3.4
—
ns
—
48
ns
85
—
48
ns
—
3
ns
1. They are common for JTAG and CJTAG.
TCLK (input)
J2
J3
J3
J4
J4
Figure 6. Test clock input timing
K20 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
26
Preliminary
Freescale Semiconductor, Inc.