K20P144M120SF3 Datasheet, PDF (49/80 Pages) Freescale Semiconductor, Inc – K20 Sub-Family Data Sheet

6.6.1.3
Peripheral operating requirements and behaviors
16-bit ADC with PGA operating conditions
Table 29. 16-bit ADC with PGA operating conditions
Symbol
V_DDA
V_REFPGA
Description
Supply voltage
PGA ref voltage
Conditions
Absolute
V_ADIN
V_CM
R_PGAD
R_AS
T_S
C_rate
Input voltage
Input Common
Mode range
Differential input
impedance
Gain = 1, 2, 4, 8
Gain = 16, 32
Gain = 64
Analog source
resistance
ADC sampling
time
ADC conversion
rate
≤ 13 bit modes
No ADC hardware
averaging
Continuous
conversions enabled
Peripheral clock = 50
MHz
16 bit modes
No ADC hardware
averaging
Continuous
conversions enabled
Peripheral clock = 50
MHz
Min.
Typ.¹
Max.
1.71
—
3.6
VREF_OU VREF_OU VREF_OU
T
T
T
V_SSA
—
V_DDA
V_SSA
—
V_DDA
—
128
—
—
64
—
—
32
—
—
100
—
1.25
—
—
18.484
—
450
37.037
—
250
Unit
V
V
V
V
kΩ
Ω
µs
Ksps
Ksps
Notes
2, 3
IN+ to IN-⁴
5
6
7
8
1. Typical values assume V_DDA = 3.0 V, Temp = 25°C, f_ADCK = 6 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. ADC must be configured to use the internal voltage reference (VREF_OUT)
3. PGA reference is internally connected to the VREF_OUT pin. If the user wishes to drive VREF_OUT with a voltage other
than the output of the VREF module, the VREF module must be disabled.
4. For single ended configurations the input impedance of the driven input is R_PGAD/2
5. The analog source resistance (R_AS), external to MCU, should be kept as minimum as possible. Increased R_AS causes drop
in PGA gain without affecting other performances. This is not dependent on ADC clock frequency.
6. The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25µs
time should be allowed for F_in=4 kHz at 16-bit differential mode. Recommended ADC setting is: ADLSMP=1, ADLSTS=2 at
8 MHz ADC clock.
7. ADC clock = 18 MHz, ADLSMP = 1, ADLST = 00, ADHSC = 1
8. ADC clock = 12 MHz, ADLSMP = 1, ADLST = 01, ADHSC = 1
K20 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
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