K20P144M120SF3 Datasheet, PDF (22/80 Pages) Freescale Semiconductor, Inc – K20 Sub-Family Data Sheet

General
Table 9. Device clock specifications (continued)
Symbol
f_BUS
FB_CLK
f_FLASH
f_LPTMR
Description
Bus clock
FlexBus clock
Flash clock
LPTMR clock
Min.
—
—
—
—
Max.
4
4
1
4
Unit
MHz
MHz
MHz
MHz
Notes
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any
other module.
5.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
CAN, CMT, and I²C signals.
Table 10. General switching specifications
Symbol
t_io50
Description
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
External reset pulse width (digital glitch filter disabled)
Mode select (EZP_CS) hold time after reset
deassertion
Port rise and fall time (high drive strength)
• Slew disabled
• Slew enabled
Min.
1.5
100
16
100
2
—
—
Max.
—
—
—
—
—
TBD
TBD
Unit
Bus clock
cycles
ns
ns
ns
Bus clock
cycles
ns
ns
Notes
1
2
2
2
3
4
t_io50
Port rise and fall time (low drive strength)
• Slew disabled
• Slew enabled
—
TBD
ns
3
—
TBD
ns
4
t_io60
Port rise and fall time (high drive strength)
• Slew disabled
• Slew enabled
—
TBD
ns
3
—
TBD
ns
4
t_io60
Port rise and fall time (low drive strength)
• Slew disabled
• Slew enabled
—
TBD
ns
3
—
TBD
ns
4
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
22
Preliminary
Freescale Semiconductor, Inc.