K20P144M120SF3 Datasheet, PDF (40/80 Pages) Freescale Semiconductor, Inc – K20 Sub-Family Data Sheet

Peripheral operating requirements and behaviors
NFC_CEn
NFC_RE
NFC_IOn
NFC_RB
tRC
tRP tREH
tIS
data
data
tRR
tCH
data
Figure 14. Read data latch cycle timing in non-fast mode
NFC_CEn
NFC_RE
NFC_IOn
NFC_RB
tRC
tRP tREH
tIS
data
data
tRR
tCH
data
Figure 15. Read data latch cycle timing in fast mode
6.4.4 Flexbus Switching Specifications
All processor bus timings are synchronous; input setup/hold and output delay are given in
respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be
the same as the internal system bus frequency or an integer divider of that frequency.
The following timing numbers indicate when data is latched or driven onto the external
bus, relative to the Flexbus output clock (FB_CLK). All other timing relationships can be
derived from these values.
Table 25. Flexbus limited voltage range switching specifications
Num
FB1
Description
Operating voltage
Frequency of operation
Clock period
Min.
2.7
—
20
Max.
3.6
FB_CLK
—
Unit
V
MHz
ns
Notes
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
40
Preliminary
Freescale Semiconductor, Inc.