K20P144M120SF3 Datasheet, PDF (61/80 Pages) Freescale Semiconductor, Inc – K20 Sub-Family Data Sheet

Peripheral operating requirements and behaviors
USB_CLKIN
U2
ULPI_DIR/ULPI_NXT
(control input)
ULPI_DATAn (input)
ULPI_STP
(control output)
ULPI_DATAn (output)
U1
U3
U4
U5
Figure 25. ULPI timing diagram
6.8.5 CAN switching specifications
See General switching specifications.
6.8.6 DSPI switching specifications (limited voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provide DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Num
DS1
DS2
DS3
DS4
Table 41. Master mode DSPI timing (limited voltage range)
Operating voltage
Description
Frequency of operation
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
DSPI_SCK to DSPI_PCSn invalid delay
Min.
Max.
2.7
3.6
—
30
2 x t_BUS
—
(t_SCK/2) − 2 (t_SCK/2) + 2
(t_BUS x 2) −
—
2
(t_BUS x 2) −
—
2
Unit
V
MHz
ns
ns
ns
ns
Table continues on the next page...
Notes
1
2
K20 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
61