908E621_12 Datasheet, PDF (56/60 Pages) Freescale Semiconductor, Inc – Integrated Quad Half bridge and Triple High Side Embedded MCU and LIN for High End Mirror

ADDITIONAL INFORMATION
THERMAL ADDENDUM (REV 1.0)
ADDITIONAL INFORMATION
THERMAL ADDENDUM (REV 1.0)
908E621
INTEGRATED QUAD H-BRIDGE AND TRIPLE HIGH-SIDE DRIVER
WITH EMBEDDED MCU AND LIN FOR MIRROR
Introduction
This thermal addendum is provided as a supplement to the MM908E621
technical data sheet. The addendum provides thermal performance information
that may be critical in the design and development of system applications. All
electrical, application and packaging information is provided in the data sheet.
Package and Thermal Considerations
This MM908E621 is a dual die package. There are two heat sources in the
package independently heating with P₁ and P₂. This results in two junction
temperatures, T_J1 and T_J2, and a thermal resistance matrix with R_θJAmn.
For m, n = 1, R_θJA11 is the thermal resistance from Junction 1 to the reference
temperature while only heat source 1 is heating with P₁.
For m = 1, n = 2, R_θJA12 is the thermal resistance from Junction 1 to the
reference temperature while heat source 2 is heating with P₂. This applies to
R_θJ21 and R_θJ22, respectively.
T_J1
T_J2
=
R_θJA11 R_{θJA12 .} P₁
R_θJA21 R_θJA22
P₂
54-PIN
SOICW-EP
98ASA10712D
54-PIN SOICW-EP
Note For package dimensions, refer to the
908E621 device datasheet.
The stated values are solely for a thermal performance comparison of one
package to another in a standardized environment. This methodology is not meant to and will not predict the performance of a
package in an application-specific environment. Stated values were obtained by measurement and simulation according to the
standards listed below.
Standards
Table 22. Thermal Performance Comparison
Thermal
Resistance
R_θJAmn ⁽¹⁾⁽²⁾
R_θJBmn ⁽²⁾⁽³⁾
R_θJAmn ⁽¹⁾⁽⁴⁾
R_θJCmn ⁽⁵⁾
1 = Power Chip, 2 = Logic Chip [°C/W]
m = 1,
n=1
m = 1, n = 2
m = 2, n = 1
m = 2,
n=2
23
20
24
9.0
6.0
10
52
47
52
1.0
0
2.0
Notes:
1. Per JEDEC JESD51-2 at natural convection, still air
condition.
2. 2s2p thermal test board per JEDEC JESD51-7and
JESD51-5.
3. Per JEDEC JESD51-8, with the board temperature on the
center trace near the power outputs.
4. Single layer thermal test board per JEDEC JESD51-3 and
JESD51-5.
5. Thermal resistance between the die junction and the
exposed pad, “infinite” heat sink attached to exposed pad.
1.0
1.0
0.2
0.2
* All measurements
are in millimeters
Soldermast
openings
Thermal vias
connected to top
54 Terminal SOIC-EP
buried plane
0.65 mm Pitch
17.9 mm x 7.5 mm Body
10.3 mm x 5.1 mm Exposed Pad
Figure 34. Thermal Land Pattern for Direct Thermal
Attachment Per JEDEC JESD51-5
908E621
56
Analog Integrated Circuit Device Data
Freescale Semiconductor