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908E621_12 Datasheet, PDF (50/60 Pages) Freescale Semiconductor, Inc – Integrated Quad Half bridge and Triple High Side Embedded MCU and LIN for High End Mirror
TYPICAL APPLICATIONS
.
VSUP
+
47µF
100nF
VSUP[1:8]
GND[1:4]
VDD
VDD
VSS
VDD
RS232
DB-9
2
3
5
1 C1+
+
1µF
VCC 16
3 C1-
GND 15
4 C2+
V+ 2
+
1µF
V- 6
5 C2- MAX232
+
1µF
1µF
+
1µF
+
7 T2OUT
8 R2IN
T2IN 10
74HC125
R2OUT 9 2
3
1
74HC125
6
5
4
VDD
10k
RST
RST_A
VDDA/VREFH
EVDD
100nF
VTST
IRQ
VSSA/VREFL
IRQ_A MM908E621 EVSS
9.8304MHz CLOCK
CLK PTC4/OSC1
DATA PTA0/KBD0
10k
TESTMODE
10k
PTB4/AD4
10k
PTA1/KBD1
10k
PTB3/AD3
4.7µF
VDD
Figure 31. Normal Monitor Mode Circuit
Table 20 summarizes the possible configurations and the
necessary setups.
Table 20. Monitor Mode Signal Requirements and Options
Serial
Mode
Mode
IRQ RST TESTMODE
Reset
Vector
Communication
Selection
ICG
PTA0 PTA1 PTB3 PTB4
COP
Normal
Communication Speed
Request
Time-out External Bus
Baud
Clock Frequency Rate
Normal
Monitor
VTST
VDD
1
X
1
0
0
1
OFF disabled disabled
9.8304
MHz
2.4576
MHz
9600
VDD
Forced
Monitor
VDD
1
GND
$FFFF
(blank)
1
0
OFF disabled disabled
9.8304
MHz
2.4576
MHz
9600
X
X
ON disabled disabled
—
Nominal Nominal
1.6 MHz 6300
User VDD VDD
not $FFFF
0
X
(not blank)
X
X
X
ON enabled enabled
—
Nominal Nominal
1.6 MHz 6300
Notes
36. PTA0 must have a pullup resistor to VDD in monitor mode
37. External clock is a 4.9152 MHz, 9.8304 MHz or 19.6608 MHz canned oscillator on OCS1
38. Communication speed with external clock is depending on external clock value. Baud rate is bus frequency / 256
39. X = don’t care
40. VTST is a high voltage VDD + 3.5 V ≤ VTST ≤ VDD + 4.5 V
EMC/EMI RECOMMENDATIONS
This paragraph gives some device specific
recommendations to improve EMC/EMI performance.
Further generic design recommendations can be found on
the Freescale web site www.freescale.com.
VSUP Pins (VSUP[1:8])
It is recommended to place a high quality ceramic
decoupling capacitor close to the VSUP pins to improve
EMC/EMI behavior.
908E621
50
Analog Integrated Circuit Device Data
Freescale Semiconductor