908E621_12 Datasheet, PDF (42/60 Pages) Freescale Semiconductor, Inc – Integrated Quad Half bridge and Triple High Side Embedded MCU and LIN for High End Mirror

FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Table 10. LIN Slew Rate Selection Bits
SRS1
SRS0
Slew rate
0
0
Initial Slew Rate (20 kBaud)
0
1
High Speed II (8x)
1
0
Slow Slew Rate (10 kBaud)
1
1
High Speed I (4x)
The high speed slew rates are used, for example, for
programming via the LIN, and are not intended for use in the
application.
System Status Register (SYSSTAT)
Register Name and Address: SYSSTAT - $0C
Bit7 6
5
4
3
2
1 Bit0
Read LINC HTIF VF H0F HVD HSF HBF 0
L
DF
Write
Reset 0
0
0
0
0
0
0
0
LINCL — LIN Current Limitation Bit
This read only bit is set if the LIN transmitter operates in
current limitation region. Due to excessive power dissipation
in the transmitter, the driver will be automatically turned off
after a certain time.
1 = transmitter operating in current limitation region
0 = transmitter not operating in current limitation region
HTIF— Over-temperature Status Bit
This read only bit is a copy of the HTIF bit in the Interrupt
Flag register
1 = over-temperature condition
0 = no over-temperature condition
VF — Voltage Failure Bit
This read only bit indicates that the supply voltage was out
of the allowed range. The bit is set if either the LVIF or the
HVIF in the Interrupt Flag register is set.
1 = low/high voltage condition detected
0 = no voltage failure condition detected
HVIF
VF
LVIF
Figure 25. VF Flag Generation
H0F — H0 Failure Bit
This read only bit is a copy of the H0OCF bit in the H0/L0
Status and Control Register (HLSCTL)
1 = over-current detected on H0
0 = no over-current on H0
908E621
42
HVDDF— HVDD Failure Bit
This read only bit is a copy of the HVDDOCF bit in the High
Side Status register
1 = HVDD pin fail
0 = HVDD normal operating
HSF— HS1:3 Failure Bit
This read only bit is set if a fail condition on one of the high
side outputs is present
1 = HS1:3 pin fail
0 = HS1:3 normal operating
HS1OCF
HS2OCF
HS3OCF
HSF
Figure 26. HSF Flag Generation
HBF— HB1:4 Failure Bit
This read only bit is set if a fail condition on one of the half-
bridge outputs is present.
1 = HB1:4 pin over-current fail
0 = HB1:4 normal operating
HB1OCF
HB2OCF
HB3OCF
HB4OCF
HBF
Figure 27. HBF Flag Generation
WINDOW WATCHDOG
The window watchdog is used to supervise the device, and
to recover from, e.g. code runaways, or similar conditions.
The use of a window watchdog adds additional safety, as
the watchdog clear has not only to occur, but be done at a
certain time frame / window.
Normal mode
The window watchdog function is only available in Normal
mode, and is halted in Stop and Sleep mode. On setting the
WDRE bit, the watchdog functionality is activated. Once this
function is enabled, it is not possible to disable it via software.
Reset clears the WDRE bit.
To prevent a Watchdog reset, the Watchdog timer has to
be cleared in the Window Open frame. This is done by writing
a logic “1” to the WDRST bit in the Watchdog Control register
(WDCTL). The actual reset of the watchdog counter occurs at
the end of the corresponding SPI transmission, with the rising
edge of the SS signal.
Analog Integrated Circuit Device Data
Freescale Semiconductor